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ac,radeonsi: simplify checking for Navi1x chips

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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4698>
This commit is contained in:
Marek Olšák 2020-03-26 21:48:48 -04:00 • committed by Marge Bot
parent d8443b211e
commit b4fd8f1919
5 changed files with 10 additions and 21 deletions
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5
src/amd/llvm/ac_llvm_build.c
View file

@ -4818,10 +4818,7 @@ void ac_build_sendmsg_gs_alloc_req(struct ac_llvm_context *ctx, LLVMValueRef wav
* We always have to export at least 1 primitive.
* Export a degenerate triangle using vertex 0 for all 3 vertices.
*/
if (prim_cnt == ctx->i32_0 &&
(ctx->family == CHIP_NAVI10 ||
ctx->family == CHIP_NAVI12 ||
ctx->family == CHIP_NAVI14)) {
if (prim_cnt == ctx->i32_0 && ctx->chip_class == GFX10) {
assert(vtx_cnt == ctx->i32_0);
prim_cnt = ctx->i32_1;
vtx_cnt = ctx->i32_1;

5
src/gallium/drivers/radeonsi/si_shader_llvm_vs.c
View file

@ -664,11 +664,10 @@ void si_llvm_build_vs_exports(struct si_shader_context *ctx,
if (pos_args[i].out[0])
shader->info.nr_pos_exports++;
/* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
/* GFX10 (Navi1x) skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
* Setting valid_mask=1 prevents it and has no other effect.
*/
if (ctx->screen->info.family == CHIP_NAVI10 || ctx->screen->info.family == CHIP_NAVI12 ||
ctx->screen->info.family == CHIP_NAVI14)
if (ctx->screen->info.chip_class == GFX10)
pos_args[0].valid_mask = 1;
pos_idx = 0;

4
src/gallium/drivers/radeonsi/si_state.c
View file

@ -584,7 +584,7 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx,
blend->blend_enable_4bit |= 0xfu << (i * 4);
if (sctx->chip_class >= GFX8 && sctx->family <= CHIP_NAVI14)
if (sctx->chip_class >= GFX8 && sctx->chip_class <= GFX10)
blend->dcc_msaa_corruption_4bit |= 0xfu << (i * 4);
/* This is only important for formats without alpha. */
@ -595,7 +595,7 @@ static void *si_create_blend_state_mode(struct pipe_context *ctx,
blend->need_src_alpha_4bit |= 0xfu << (i * 4);
}
if (sctx->chip_class >= GFX8 && sctx->family <= CHIP_NAVI14 && logicop_enable)
if (sctx->chip_class >= GFX8 && sctx->chip_class <= GFX10 && logicop_enable)
blend->dcc_msaa_corruption_4bit |= blend->cb_target_enabled_4bit;
if (blend->cb_target_mask) {

13
src/gallium/drivers/radeonsi/si_state_shaders.c
View file

@ -918,8 +918,7 @@ static void gfx10_emit_ge_pc_alloc(struct si_context *sctx, unsigned value)
sctx->tracked_regs.reg_value[reg] != value) {
struct radeon_cmdbuf *cs = sctx->gfx_cs;
if (sctx->family == CHIP_NAVI10 || sctx->family == CHIP_NAVI12 ||
sctx->family == CHIP_NAVI14) {
if (sctx->chip_class == GFX10) {
/* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
@ -1162,8 +1161,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
/* Limit LATE_ALLOC_GS for prevent a hang (hw bug). */
if (sscreen->info.family == CHIP_NAVI10 || sscreen->info.family == CHIP_NAVI12 ||
sscreen->info.family == CHIP_NAVI14)
if (sscreen->info.chip_class == GFX10)
late_alloc_wave64 = MIN2(late_alloc_wave64, 64);
si_pm4_set_reg(
@ -1255,8 +1253,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
*
* Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
*/
if ((sscreen->info.family == CHIP_NAVI10 || sscreen->info.family == CHIP_NAVI12 ||
sscreen->info.family == CHIP_NAVI14) &&
if ((sscreen->info.chip_class == GFX10) &&
(es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
shader->ngg.hw_max_esverts != 256) {
shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
@ -2950,9 +2947,7 @@ bool si_update_ngg(struct si_context *sctx)
* VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
* pointers are set.
*/
if ((sctx->family == CHIP_NAVI10 || sctx->family == CHIP_NAVI12 ||
sctx->family == CHIP_NAVI14) &&
!new_ngg)
if (sctx->chip_class == GFX10 && !new_ngg)
sctx->flags |= SI_CONTEXT_VGT_FLUSH;
sctx->ngg = new_ngg;

4
src/gallium/drivers/radeonsi/si_texture.c
View file

@ -1259,9 +1259,7 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
/* Stencil texturing with HTILE doesn't work
* with mipmapping on Navi10-14. */
if ((sscreen->info.family == CHIP_NAVI10 || sscreen->info.family == CHIP_NAVI12 ||
sscreen->info.family == CHIP_NAVI14) &&
base->last_level > 0)
if (sscreen->info.chip_class == GFX10 && base->last_level > 0)
tex->htile_stencil_disabled = true;
} else {
tex->can_sample_z = !tex->surface.u.legacy.depth_adjusted;