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Author SHA1 Message Date
Kenneth Graunke
3f70956a4e iris: try and avoid pointless compute submissions 
if apps don't use compute shaders, we don't even want to kick off the
compute initialization batch
 2019-02-21 10:26:09 -08:00
Kenneth Graunke
97125e9bb3 iris: fix SBA flushing by refactoring code 2019-02-21 10:26:09 -08:00
Kenneth Graunke
8fa99481e7 iris: do PIPELINE_SELECT for render engine, add flushes, GLK hacks 2019-02-21 10:26:09 -08:00
Kenneth Graunke
b2d223b6bf iris: hack to avoid memorybarriers out the wazoo 
we don't want to emit piles of pipe controls to a compute batch if
it isn't necessary...

prevents double-batch-wraps in cs-op-selection-bool-bvec4-bvec4
(but it's still kinda a big ol' hack...)
 2019-02-21 10:26:09 -08:00
Kenneth Graunke
b3a40c27a2 iris: don't let render/compute contexts stomp each other's dirty bits 
only clear what you process
 2019-02-21 10:26:09 -08:00
Kenneth Graunke
f8796079da iris: better dirty checking 2019-02-21 10:26:09 -08:00
Kenneth Graunke
06a993dac2 iris: rewrite grid surface handling 
now we only upload a new grid when it's actually changed, which saves us
from having to emit a new binding table every time it changes.

this also moves a bunch of non-gen-specific stuff out of iris_state.c
 2019-02-21 10:26:09 -08:00
Kenneth Graunke
155e1a63d5 iris: XXX for compute state tracking :/ 
Maybe we should just move dirty to batch, it would help with the
reset stuff too
 2019-02-21 10:26:09 -08:00
Kenneth Graunke
643030f4fb iris: fix whitespace 2019-02-21 10:26:09 -08:00
Kenneth Graunke
b0dc11993e iris: bail if SLM is needed 2019-02-21 10:26:09 -08:00
Kenneth Graunke
973b937cac iris: leave XXX about unnecessary binding table uploads 2019-02-21 10:26:09 -08:00
Kenneth Graunke
7fb8c20d7b iris: drop unnecessary #ifdefs 2019-02-21 10:26:09 -08:00
Kenneth Graunke
549db5b90e iris: drop XXX that Jordan handled 2019-02-21 10:26:09 -08:00
Jordan Justen
942bdb2906 iris/compute: Support indirect compute dispatch 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
 2019-02-21 10:26:09 -08:00
Jordan Justen
b35c8f2182 iris/compute: Push subgroup-id 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
 2019-02-21 10:26:09 -08:00
Jordan Justen
229450a2a6 iris/compute: Flush compute batch on memory-barriers 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
 2019-02-21 10:26:09 -08:00
Jordan Justen
fb4637797e iris/compute: Provide binding table entry for gl_NumWorkGroups 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
 2019-02-21 10:26:09 -08:00
Jordan Justen
fcd0364857 iris/compute: Wait on compute batch when mapping 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
 2019-02-21 10:26:09 -08:00
Jordan Justen
ea416d0b5d iris/program: Don't try to push ubo ranges for compute 
We only can push constants for compute shaders from one range.

Gallium glsl-to-nir (src/mesa/state_tracker/st_glsl_to_nir.cpp) lowers
all uniform accesses to a ubo.

Unfortunately we also load the subgroup-id as a uniform in the
compiler. Since we use the 1 push range for this subgroup-id, we then
lose the ability to actually push the ubo with all the normal user
uniform values.

In other words, there is lots of room for performance improvement, but
at least retrieving the uniforms as pull-constants is functional for
now.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
 2019-02-21 10:26:09 -08:00
Jordan Justen
c7cfa4000f iris/compute: Get group counts from grid->grid 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
 2019-02-21 10:26:09 -08:00
Jordan Justen
fd9ccd8b5d iris/compute: Flush compute batches 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
 2019-02-21 10:26:09 -08:00
Jordan Justen
9b5cda95aa iris/compute: Add MEDIA_STATE_FLUSH following WALKER 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
 2019-02-21 10:26:09 -08:00
Jordan Justen
6ebd04ac8f iris: Add iris_restore_compute_saved_bos 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
 2019-02-21 10:26:09 -08:00
Jordan Justen
622aaa290f iris: Add IRIS_DIRTY_CONSTANTS_CS 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
 2019-02-21 10:26:09 -08:00
Jordan Justen
25f1625edf iris/compute: Set mask bits on PIPELINE_SELECT 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
 2019-02-21 10:26:09 -08:00
Kenneth Graunke
9fc672428d iris: little bits of compute basics 2019-02-21 10:26:09 -08:00
Kenneth Graunke
860ce6af3f iris: drop XXX's about swizzling 
pretty sure this is unnecessary on modern HW
 2019-02-21 10:26:09 -08:00
Kenneth Graunke
12de56f53d iris: drop dead format //'s 
these just aren't supported
 2019-02-21 10:26:09 -08:00
Kenneth Graunke
f6c68066a6 iris: yes 2019-02-21 10:26:09 -08:00
Kenneth Graunke
752abeb690 iris: initial compute caps 
RET macro borrowed from freedreno
 2019-02-21 10:26:09 -08:00
Kenneth Graunke
4da28c2c22 iris: Enable fb fetch 
needed for ES 3.2
 2019-02-21 10:26:09 -08:00
Kenneth Graunke
be905bd461 iris: advertise GL_ARB_shader_texture_image_samples 2019-02-21 10:26:09 -08:00
Jordan Justen
6441e906e8 iris: Set num_uniforms in bytes 
Ref: brw_nir_lower_uniforms, type_size_scalar_bytes

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
 2019-02-21 10:26:09 -08:00
Kenneth Graunke
c29fd34259 iris: move images next to textures in binding table 2019-02-21 10:26:09 -08:00
Kenneth Graunke
0d9c5b4e7e iris: null for non-existent cbufs 
prevents BTs from being shifted down incorrectly
 2019-02-21 10:26:09 -08:00
Kenneth Graunke
98e8f80e7d iris: actually set image access 2019-02-21 10:26:09 -08:00
Jason Ekstrand
d9aee25a46 iris: Don't lower image formats for write-only images 2019-02-21 10:26:09 -08:00
Kenneth Graunke
a06f0fe517 iris: set image access correctly 2019-02-21 10:26:09 -08:00
Kenneth Graunke
5d1dadfc38 iris: bother with BTIs 2019-02-21 10:26:09 -08:00
Kenneth Graunke
f5b887da6c iris: implement set_shader_images hook 2019-02-21 10:26:09 -08:00
Kenneth Graunke
26a54ae4b2 iris: lower storage image derefs 2019-02-21 10:26:09 -08:00
Kenneth Graunke
e97a24da89 iris: set the binding table size 
we weren't doing mark_surface_used on images (i965 does it while
uploading the unnecessary image uniforms), so our binding tables were
too small...
 2019-02-21 10:26:09 -08:00
Kenneth Graunke
28b41992c8 iris: X32_S8X24 :/ 
This can happen when faking Z32_S8X24 and setting StencilSampling = true

I guess we'll just turn it into S8_UINT...

Fixes KHR-GL45.texture_swizzle.functional
 2019-02-21 10:26:09 -08:00
Kenneth Graunke
6e7957a22d iris: enable I/L formats 2019-02-21 10:26:09 -08:00
Kenneth Graunke
bfbebbaa36 iris: Use R/RG instead of I/L/A when sampling 2019-02-21 10:26:09 -08:00
Kenneth Graunke
94569a6458 iris: rework format translation apis 2019-02-21 10:26:09 -08:00
Kenneth Graunke
b9eeed3e8f iris: Allow PIPE_CONTROL with Stall at Scoreboard and RT flush 
It's nonsensical, but not illegal, and mandatory on Icelake
 2019-02-21 10:26:09 -08:00
Kenneth Graunke
65d1cda995 iris: add gen11 to genX_call 2019-02-21 10:26:09 -08:00
Kenneth Graunke
0fdcb20803 iris: inline stage_from_pipe to avoid unused warnings 2019-02-21 10:26:09 -08:00
Kenneth Graunke
6fbb6ba290 iris: pipe to scs -> iris_pipe.h 2019-02-21 10:26:09 -08:00