There's no reason to have the checksum_bo at the slice level since there
can only be one external CRC BO per resource. Move this field to the
panfrost_resource struct.
Suggested-by: Icecream95
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
Similar to shared memory load/store, except giving a different memory
type to the hardware.
Add nir->scratch_size to ctx->tls_size to allocate the memory.
Tested with the Piglit OpenCL test i32-stack-array.cl.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8264>
There are now more intrinsics for which nir_type_uint is forced than
where the destination type is used to find the intrinsic type, so
invert the conditional so that nir_type_uint is the default case when
nothing more specific is given.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8264>
We want to add support for more memory types, so replace the is_shared
bool with an integer that is directly stored to load_store.arg_1.
The new memory type values are off by 0x40, as that bit now comes from
the index type.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8264>
mir_args_ssa asserted that the given number of arguments to use is
greater than or equal to the actual number, but this is not checked by
callers, so instead of crashing return false to mark failure.
Fixes the local memory atomics OpenCL tests in Piglit.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8264>
The index type is actually a two-bit field, with support for both sign
and zero extension.
What was previously labelled as `zext` actually does sign-extension,
but we want that in most cases anyway.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8264>
NIR generates global_invocation_id, but Clover lowers it to
global_invocation_id_zero_base. It isn't lowered for OpenGL,
so we need to support both intrinsics.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8264>
The bound parameter allows us to prevent allocations from crossing
particular boundaries (typically 128-bit boundaries). For 16-bit, we
don't want to cross 64-bit boundaries, in order to keep swizzles
possible to encode. We already handle this for 16-bit destinations, but
it _also_ needs to be (redundantly) handled for 16-bit sources, in case
types don't match (for example, with a vectorized size conversion
instruction).
Fixes a few newer dEQP fails.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8282>
The ATEST FAU index must point to the ATEST parameter datum slot
otherwise the cmdstream config is ignored.
(Rebased by Alyssa)
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8135>
A given tuple can only load a single entry from FAU-RAM, so we need a
lowering pass before scheduling to assign FAU and lower the other
sources to moves.
Right now this only handles constants. Uniforms and general FAU are
todo.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8135>
We'll let the routines coexist for a moment, just to keep the commits
digestible, but this is modified from bi_make_singleton.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8135>
Generates bi_index from nir_alu_src, taking into account the applied
swizzle, and using (swizzle / 32-bit) portion as an offset, to be
applied later during RA. The sub 32-bit portion only applies for 8-bit
and 16-bit instructions, which need to either handle them explicitly as
a swizzle specifier, or lower to a swizzle explicitly.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8135>
