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pan/bi: Implement ALU with the builder
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8135>
This commit is contained in:
Alyssa Rosenzweig
Marge Bot
parent
8e82641cf5
commit
f05174e5a5
1 changed files with 396 additions and 0 deletions
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@ -2075,6 +2075,402 @@ bi_cmpf_nir(nir_op op)
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}
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}
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static void
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bi_emit_alu(bi_builder *b, nir_alu_instr *instr)
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{
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bi_index dst = bi_dest_index(&instr->dest.dest);
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unsigned sz = nir_dest_bit_size(instr->dest.dest);
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unsigned srcs = nir_op_infos[instr->op].num_inputs;
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unsigned comps = nir_dest_num_components(instr->dest.dest);
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if (!instr->dest.dest.is_ssa) {
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for (unsigned i = 0; i < comps; ++i)
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assert(instr->dest.write_mask);
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}
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/* First, match against the various moves in NIR. These are
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* special-cased because they can operate on vectors even after
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* lowering ALU to scalar. For Bifrost, bi_alu_src_index assumes the
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* instruction is no "bigger" than SIMD-within-a-register. These moves
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* are the exceptions that need to handle swizzles specially. */
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switch (instr->op) {
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case nir_op_vec2:
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case nir_op_vec3:
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case nir_op_vec4: {
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bi_index unoffset_srcs[4] = {
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srcs > 0 ? bi_src_index(&instr->src[0].src) : bi_null(),
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srcs > 1 ? bi_src_index(&instr->src[1].src) : bi_null(),
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srcs > 2 ? bi_src_index(&instr->src[2].src) : bi_null(),
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srcs > 3 ? bi_src_index(&instr->src[3].src) : bi_null(),
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};
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unsigned channels[4] = {
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instr->src[0].swizzle[0],
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instr->src[1].swizzle[0],
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srcs > 2 ? instr->src[2].swizzle[0] : 0,
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srcs > 3 ? instr->src[3].swizzle[0] : 0,
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};
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bi_make_vec_to(b, dst, unoffset_srcs, channels, srcs, sz);
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return;
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}
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case nir_op_vec8:
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case nir_op_vec16:
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unreachable("should've been lowered");
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case nir_op_mov: {
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bi_index idx = bi_src_index(&instr->src[0].src);
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bi_index unoffset_srcs[4] = { idx, idx, idx, idx };
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unsigned channels[4] = {
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comps > 0 ? instr->src[0].swizzle[0] : 0,
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comps > 1 ? instr->src[0].swizzle[1] : 0,
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comps > 2 ? instr->src[0].swizzle[2] : 0,
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comps > 3 ? instr->src[0].swizzle[3] : 0,
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};
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bi_make_vec_to(b, dst, unoffset_srcs, channels, comps, sz);
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return;
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}
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default:
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break;
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}
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bi_index s0 = srcs > 0 ? bi_alu_src_index(instr->src[0], comps) : bi_null();
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bi_index s1 = srcs > 1 ? bi_alu_src_index(instr->src[1], comps) : bi_null();
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bi_index s2 = srcs > 2 ? bi_alu_src_index(instr->src[2], comps) : bi_null();
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unsigned src_sz = srcs > 0 ? nir_src_bit_size(instr->src[0].src) : 0;
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switch (instr->op) {
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case nir_op_ffma:
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bi_fma_to(b, sz, dst, s0, s1, s2, BI_ROUND_NONE);
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break;
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case nir_op_fmul:
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bi_fma_to(b, sz, dst, s0, s1, bi_zero(), BI_ROUND_NONE);
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break;
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case nir_op_fsub:
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s1 = bi_neg(s1);
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/* fallthrough */
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case nir_op_fadd:
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bi_fadd_to(b, sz, dst, s0, s1, BI_ROUND_NONE);
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break;
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case nir_op_fsat: {
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bi_instr *I = (sz == 32) ?
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bi_fadd_f32_to(b, dst, s0, bi_zero(), BI_ROUND_NONE) :
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bi_fma_v2f16_to(b, dst, s0, bi_zero(), bi_zero(),
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BI_ROUND_NONE);
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I->clamp = BI_CLAMP_CLAMP_0_1;
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break;
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}
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case nir_op_fneg:
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bi_fadd_to(b, sz, dst, bi_neg(s0), bi_zero(), BI_ROUND_NONE);
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break;
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case nir_op_fabs:
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bi_fadd_to(b, sz, dst, bi_abs(s0), bi_zero(), BI_ROUND_NONE);
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break;
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case nir_op_fexp2: {
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/* TODO G71 */
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assert(sz == 32); /* should've been lowered */
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/* multiply by 1.0 * 2*24 */
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bi_index scale = bi_fma_rscale_f32(b, s0, bi_imm_f32(1.0f),
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bi_zero(), bi_imm_u32(24), BI_ROUND_NONE,
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BI_SPECIAL_NONE);
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bi_fexp_f32_to(b, dst, bi_f32_to_s32(b, scale, BI_ROUND_NONE), s0);
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break;
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}
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case nir_op_flog2: {
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/* TODO G71 */
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assert(sz == 32); /* should've been lowered */
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bi_index frexp = bi_frexpe_f32(b, s0, true, false);
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bi_index frexpi = bi_s32_to_f32(b, frexp, BI_ROUND_RTZ);
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bi_index add = bi_fadd_lscale_f32(b, bi_imm_f32(-1.0f), s0);
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bi_fma_f32_to(b, dst, bi_flogd_f32(b, s0), add, frexpi,
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BI_ROUND_NONE);
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break;
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}
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case nir_op_b8csel:
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case nir_op_b16csel:
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case nir_op_b32csel:
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if (sz == 8)
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bi_mux_v4i8_to(b, dst, s2, s1, s0, BI_MUX_INT_ZERO);
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else
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bi_csel_to(b, sz, dst, s0, bi_zero(), s1, s2, BI_CMPF_NE);
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break;
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case nir_op_ishl:
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bi_lshift_or_to(b, sz, dst, s0, bi_zero(), bi_byte(s1, 0));
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break;
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case nir_op_ushr:
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bi_rshift_or_to(b, sz, dst, s0, bi_zero(), bi_byte(s1, 0));
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break;
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case nir_op_ishr:
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bi_arshift_to(b, sz, dst, s0, bi_null(), bi_byte(s1, 0));
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break;
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case nir_op_flt32:
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case nir_op_fge32:
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case nir_op_feq32:
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case nir_op_fneu32:
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bi_fcmp_to(b, sz, dst, s0, s1, bi_cmpf_nir(instr->op),
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BI_RESULT_TYPE_M1);
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break;
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case nir_op_ieq32:
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case nir_op_ine32:
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if (sz == 32) {
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bi_icmp_i32_to(b, dst, s0, s1, bi_cmpf_nir(instr->op),
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BI_RESULT_TYPE_M1);
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} else if (sz == 16) {
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bi_icmp_v2i16_to(b, dst, s0, s1, bi_cmpf_nir(instr->op),
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BI_RESULT_TYPE_M1);
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} else {
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bi_icmp_v4i8_to(b, dst, s0, s1, bi_cmpf_nir(instr->op),
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BI_RESULT_TYPE_M1);
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}
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break;
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case nir_op_ilt32:
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case nir_op_ige32:
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if (sz == 32) {
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bi_icmp_s32_to(b, dst, s0, s1, bi_cmpf_nir(instr->op),
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BI_RESULT_TYPE_M1);
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} else if (sz == 16) {
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bi_icmp_v2s16_to(b, dst, s0, s1, bi_cmpf_nir(instr->op),
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BI_RESULT_TYPE_M1);
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} else {
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bi_icmp_v4s8_to(b, dst, s0, s1, bi_cmpf_nir(instr->op),
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BI_RESULT_TYPE_M1);
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}
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break;
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case nir_op_ult32:
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case nir_op_uge32:
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if (sz == 32) {
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bi_icmp_u32_to(b, dst, s0, s1, bi_cmpf_nir(instr->op),
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BI_RESULT_TYPE_M1);
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} else if (sz == 16) {
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bi_icmp_v2u16_to(b, dst, s0, s1, bi_cmpf_nir(instr->op),
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BI_RESULT_TYPE_M1);
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} else {
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bi_icmp_v4u8_to(b, dst, s0, s1, bi_cmpf_nir(instr->op),
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BI_RESULT_TYPE_M1);
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}
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break;
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case nir_op_fddx:
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case nir_op_fddy: {
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bi_index cur_lane = bi_mov_i32(b, bi_fau(BIR_FAU_LANE_ID, false));
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bi_index lane1 = bi_lshift_and_i32(b, cur_lane,
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bi_imm_u32(instr->op == nir_op_fddx ? 2 : 1),
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bi_byte(bi_zero(), 0));
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bi_index lane2 = bi_iadd_u32(b, lane1,
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bi_imm_u32(instr->op == nir_op_fddx ? 1 : 2),
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false);
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bi_index left, right;
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if (b->shader->arch == 6) {
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left = bi_clper_v6_i32(b, s0, lane1);
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right = bi_clper_v6_i32(b, s0, lane2);
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} else {
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left = bi_clper_v7_i32(b, s0, lane1,
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BI_INACTIVE_RESULT_ZERO, BI_LANE_OP_NONE,
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BI_SUBGROUP_SUBGROUP4);
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right = bi_clper_v7_i32(b, s0, lane2,
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BI_INACTIVE_RESULT_ZERO, BI_LANE_OP_NONE,
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BI_SUBGROUP_SUBGROUP4);
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}
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bi_fadd_to(b, sz, dst, right, bi_neg(left), BI_ROUND_NONE);
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break;
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}
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case nir_op_f2f16:
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bi_v2f32_to_v2f16_to(b, dst, s0, s0, BI_ROUND_NONE);
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break;
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case nir_op_f2f32:
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bi_f16_to_f32_to(b, dst, s0);
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break;
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case nir_op_f2i32:
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if (src_sz == 32)
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bi_f32_to_s32_to(b, dst, s0, BI_ROUND_RTZ);
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else
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bi_f16_to_s32_to(b, dst, s0, BI_ROUND_RTZ);
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break;
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case nir_op_f2u16:
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if (src_sz == 32)
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unreachable("should've been lowered");
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else
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bi_v2f16_to_v2u16_to(b, dst, s0, BI_ROUND_RTZ);
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break;
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case nir_op_f2i16:
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if (src_sz == 32)
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unreachable("should've been lowered");
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else
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bi_v2f16_to_v2s16_to(b, dst, s0, BI_ROUND_RTZ);
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break;
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case nir_op_f2u32:
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if (src_sz == 32)
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bi_f32_to_u32_to(b, dst, s0, BI_ROUND_RTZ);
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else
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bi_f16_to_u32_to(b, dst, s0, BI_ROUND_RTZ);
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break;
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case nir_op_u2f16:
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if (src_sz == 32)
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unreachable("should've been lowered");
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else if (src_sz == 16)
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bi_v2u16_to_v2f16_to(b, dst, s0, BI_ROUND_RTZ);
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else if (src_sz == 8)
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bi_v2u8_to_v2f16_to(b, dst, s0);
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break;
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case nir_op_u2f32:
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if (src_sz == 32)
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bi_u32_to_f32_to(b, dst, s0, BI_ROUND_RTZ);
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else if (src_sz == 16)
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bi_u16_to_f32_to(b, dst, s0);
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else
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bi_u8_to_f32_to(b, dst, bi_byte(s0, 0));
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break;
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case nir_op_i2f16:
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if (src_sz == 32)
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unreachable("should've been lowered");
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else
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bi_v2s16_to_v2f16_to(b, dst, s0, BI_ROUND_RTZ);
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break;
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case nir_op_i2f32:
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if (src_sz == 32)
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bi_s32_to_f32_to(b, dst, s0, BI_ROUND_RTZ);
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else
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bi_s16_to_f32_to(b, dst, s0);
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break;
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case nir_op_i2i32:
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if (src_sz == 16)
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bi_s16_to_s32_to(b, dst, s0);
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else
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bi_s8_to_s32_to(b, dst, s0);
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break;
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case nir_op_u2u32:
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if (src_sz == 16)
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bi_u16_to_u32_to(b, dst, s0);
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else
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bi_u8_to_u32_to(b, dst, s0);
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break;
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/* todo optimize out downcasts */
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case nir_op_i2i16:
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assert(src_sz == 8 || src_sz == 32);
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if (src_sz == 8)
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bi_v2s8_to_v2s16_to(b, dst, s0);
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else
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bi_mkvec_v2i16_to(b, dst, bi_half(s0, false), bi_imm_u16(0));
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break;
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case nir_op_u2u16:
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assert(src_sz == 8 || src_sz == 32);
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if (src_sz == 8)
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bi_v2u8_to_v2u16_to(b, dst, s0);
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else
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bi_mkvec_v2i16_to(b, dst, bi_half(s0, false), bi_imm_u16(0));
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break;
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case nir_op_i2i8:
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case nir_op_u2u8:
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unreachable("should've been lowered");
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case nir_op_fround_even:
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case nir_op_fceil:
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case nir_op_ffloor:
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case nir_op_ftrunc:
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bi_fround_to(b, sz, dst, s0, bi_nir_round(instr->op));
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break;
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case nir_op_fmin:
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bi_fmin_to(b, sz, dst, s0, s1);
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break;
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case nir_op_fmax:
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bi_fmax_to(b, sz, dst, s0, s1);
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break;
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case nir_op_iadd:
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bi_iadd_to(b, sz, dst, s0, s1, false);
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break;
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case nir_op_isub:
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bi_isub_to(b, sz, dst, s0, s1, false);
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break;
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case nir_op_imul:
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bi_imul_to(b, sz, dst, s0, s1);
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break;
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case nir_op_iabs:
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bi_iabs_to(b, sz, dst, s0);
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break;
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case nir_op_iand:
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bi_lshift_and_to(b, sz, dst, s0, s1, bi_imm_u8(0));
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break;
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case nir_op_ior:
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bi_lshift_or_to(b, sz, dst, s0, s1, bi_imm_u8(0));
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break;
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case nir_op_ixor:
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bi_lshift_xor_to(b, sz, dst, s0, s1, bi_imm_u8(0));
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break;
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case nir_op_inot:
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bi_lshift_or_to(b, sz, dst, bi_zero(), bi_not(s0), bi_imm_u8(0));
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break;
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case nir_op_frsq:
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bi_frsq_to(b, sz, dst, s0);
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break;
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case nir_op_frcp:
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bi_frcp_to(b, sz, dst, s0);
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break;
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default:
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fprintf(stderr, "Unhandled ALU op %s\n", nir_op_infos[instr->op].name);
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unreachable("Unknown ALU op");
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}
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}
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/* TEXS instructions assume normal 2D f32 operation but are more
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* space-efficient and with simpler RA/scheduling requirements*/
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