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Author	SHA1	Message	Date
Georg Lehmann	38e32e39a9	aco: never end wqm early for vmem ... The remaining cases where disable_wqm isn't set are either uniform loads or loads that influence control flow. In the first case, not ending WQM early is free, and in the second case it's likely still better to not block scheduling. Foz-DB GFX1201: Totals from 483 (0.60% of 80287) affected shaders: MaxWaves: 12654 -> 12642 (-0.09%) Instrs: 485234 -> 484830 (-0.08%); split: -0.19%, +0.11% CodeSize: 2630876 -> 2629184 (-0.06%); split: -0.15%, +0.08% VGPRs: 29980 -> 30004 (+0.08%) Latency: 4908015 -> 4813167 (-1.93%); split: -1.95%, +0.02% InvThroughput: 751059 -> 748582 (-0.33%); split: -0.35%, +0.02% VClause: 8723 -> 8705 (-0.21%); split: -0.30%, +0.09% SClause: 11085 -> 10986 (-0.89%); split: -1.45%, +0.56% Copies: 25155 -> 25183 (+0.11%); split: -0.26%, +0.37% Branches: 6203 -> 6204 (+0.02%) PreSGPRs: 23763 -> 23780 (+0.07%) VALU: 296576 -> 296593 (+0.01%); split: -0.01%, +0.02% SALU: 49095 -> 49416 (+0.65%); split: -0.04%, +0.69% Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36785>	2025-08-28 06:29:04 +00:00
Georg Lehmann	3d190f2e9c	aco: implement skip_helpers for load_global_amd ... Foz-DB GFX1201: Totals from 119 (0.15% of 80287) affected shaders: Instrs: 212449 -> 213452 (+0.47%) CodeSize: 1120656 -> 1124708 (+0.36%) Latency: 2854370 -> 2855772 (+0.05%); split: -0.02%, +0.07% InvThroughput: 586142 -> 586210 (+0.01%); split: -0.00%, +0.01% VClause: 3556 -> 3656 (+2.81%) SClause: 2708 -> 2710 (+0.07%) Copies: 14410 -> 14509 (+0.69%) PreSGPRs: 6810 -> 6850 (+0.59%); split: -0.12%, +0.70% VALU: 135945 -> 135942 (-0.00%); split: -0.01%, +0.01% SALU: 22147 -> 23121 (+4.40%) Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36785>	2025-08-28 06:29:04 +00:00
Georg Lehmann	ee7069f875	aco: implement skip_helpers for load_scratch ... Foz-DB GFX1201: Totals from 2 (0.00% of 80287) affected shaders: Instrs: 4016 -> 4054 (+0.95%) CodeSize: 22104 -> 22256 (+0.69%) Latency: 17123 -> 17129 (+0.04%) Copies: 406 -> 415 (+2.22%) SALU: 323 -> 353 (+9.29%) Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36785>	2025-08-28 06:29:04 +00:00
Georg Lehmann	2bfd8918a5	aco: implement skip_helpers for load_ssbo/ubo/constant ... Foz-DB GFX1201: Totals from 6676 (8.32% of 80287) affected shaders: Instrs: 8786161 -> 8829091 (+0.49%); split: -0.01%, +0.50% CodeSize: 47141800 -> 47320480 (+0.38%); split: -0.01%, +0.39% VGPRs: 376624 -> 376600 (-0.01%) SpillSGPRs: 1251 -> 1250 (-0.08%) Latency: 99716626 -> 99642361 (-0.07%); split: -0.11%, +0.04% InvThroughput: 14893179 -> 14898323 (+0.03%); split: -0.01%, +0.04% VClause: 149425 -> 153539 (+2.75%); split: -0.04%, +2.79% SClause: 251247 -> 251842 (+0.24%); split: -0.06%, +0.30% Copies: 580304 -> 586424 (+1.05%); split: -0.21%, +1.26% Branches: 163014 -> 163013 (-0.00%); split: -0.00%, +0.00% PreSGPRs: 356548 -> 357109 (+0.16%); split: -0.18%, +0.33% VALU: 5149733 -> 5149797 (+0.00%); split: -0.00%, +0.00% SALU: 1082176 -> 1122718 (+3.75%); split: -0.06%, +3.80% Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36785>	2025-08-28 06:29:03 +00:00
Georg Lehmann	bdae511b18	aco: implement skip_helpers for image loads ... Foz-DB GFX1201: Totals from 5 (0.01% of 80287) affected shaders: Instrs: 1406 -> 1417 (+0.78%) CodeSize: 8012 -> 8056 (+0.55%) Latency: 7279 -> 7282 (+0.04%) Copies: 84 -> 85 (+1.19%) SALU: 170 -> 180 (+5.88%) Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36785>	2025-08-28 06:29:02 +00:00
Georg Lehmann	bf453a7c6a	aco/isel: add init_disable_wqm helper ... Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36785>	2025-08-28 06:29:01 +00:00
Guilherme Gallo	a8a0f11953	ci/zink: Document bypassed failures ... A few failures bypassed the pipeline, since a `zink-lavapipe` job [1] misbehaved (did not run the deqp-runner tests at all), making the MR [2] merge and subsequent marge pipelines fail. [1]: https://gitlab.freedesktop.org/mesa/mesa/-/jobs/83398228 [2]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37024 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37039>	2025-08-28 01:46:05 -03:00
Mel Henning	fcf136d247	nvk: Expose VK_KHR_maintenance8 ... Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36950>	2025-08-27 21:12:41 -04:00
Mel Henning	bde5e39b41	nvk/copy: Implement CopyImage2 between R and D/S ... Following VK_KHR_maintenance8: > Allow copies between depth/stencil and “matching” color attachments Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36950>	2025-08-27 21:12:41 -04:00
Mel Henning	81e37e9c67	nvk/copy: Split out nvk_remap_copy_aspect ... Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36950>	2025-08-27 21:12:41 -04:00
Mel Henning	5e1c705bd1	nvk/copy: Split out nvk_remap_extract_aspect ... Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36950>	2025-08-27 21:12:41 -04:00
Mel Henning	caced4e028	nvk/copy: Split out nvk_remap_insert_aspect ... Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36950>	2025-08-27 21:12:41 -04:00
Caio Oliveira	84963d6833	intel/brw: Take shader in the brw_generator::generate_code() parameters ... Simplify the calls in all the stage compile functions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33541>	2025-08-28 00:06:20 +00:00
Caio Oliveira	c19a4150b5	intel/brw: Simplify variant tracking in brw_compile_fs ... Remove the cfg variables and use the shader pointers directly. Reset the variant pointer if a shader failed or will not be used. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33541>	2025-08-28 00:06:20 +00:00
Caio Oliveira	834e30d244	intel/brw: Simplify tracking of dispatch_width_limit in brw_compile_fs ... Keep it in a variable, that way don't need to check which shader to look for the limit. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33541>	2025-08-28 00:06:20 +00:00
Caio Oliveira	9d53e27579	intel/brw: Remove brw_shader::import_uniforms() ... The brw_shader::uniforms now is derived from the nir_shader. The only exception is compute shaders for older Gfx versions, so we move the adjust logic for that. The benefit here is untangling the code for compilation variants, that before needed to keep track of the first that compiled to, in most cases, copy an integer. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33541>	2025-08-28 00:06:19 +00:00
Caio Oliveira	0b4d62d340	anv: Allocate prog_data->param array when making internal kernels ... As we set prog_data->nr_params, allocate the array like elsewhere. Current code is getting by because the logic for adding a new element will realloc it. But later changes will make the array be accessed before this reallocation. This will make sure later patches won't cause tests like dEQP-VK.query_pool.statistics_query.compute_shader_invocations.32bits_cmdcopyquerypoolresults_secondary to fail in gfxver < 125. Note the bug appears when DRI option to tweak the thresold to use these shaders is set to 0. This is done by the GitLab CI, which allowed testing later patches to find this issue. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33541>	2025-08-28 00:06:19 +00:00
Caio Oliveira	b8a35a8a27	brw: Pass per_primitive_offset in brw_shader_params ... Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33541>	2025-08-28 00:06:19 +00:00
Caio Oliveira	6ca9021758	brw: Add brw_shader_params ... And unify the initialization code for brw_shader. Avoid passing brw_compile_params since for a single compilation we might have multiple shaders (the case for BS stage). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33541>	2025-08-28 00:06:18 +00:00
Pohsiang (John) Hsu	dac9360bac	mediafoundation: periodic clang-format, no code changes ... Reviewed-by: Wenfeng Gao <wenfeng@microsoft.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37035>	2025-08-27 23:18:35 +00:00
Rohit Athavale	0d2502e892	mediafoundation: Add IsSupported() & GetValue() for CODECAPI_AVEncVideoInputDeltaQPBlockSettings ... Reviewed-by: Pohsiang (John) Hsu <pohhsu@microsoft.com> Reviewed-by: Sil Vilerino <sivileri@microsoft.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37035>	2025-08-27 23:18:35 +00:00
Sil Vilerino	e47d5c1019	d3d12: Fix two pass flag setting and rate control dirty flag check ... Reviewed-by: Pohsiang (John) Hsu <pohhsu@microsoft.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37035>	2025-08-27 23:18:34 +00:00
Caio Oliveira	1c933b6511	brw: Fix checking sources of wrong instruction in opt_address_reg_load ... Fixes: 8ac7802ac8 ("brw: move final send lowering up into the IR") Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37019>	2025-08-27 22:50:23 +00:00
Lionel Landwerlin	93996c07e2	brw: fix broadcast opcode ... The problem with the current code is that there is a disconnect between : - the virtual register size allocated - the dispatch size - the size_written value Only the last 2 are in sync and this confuses the spiller that only looks at the destination register allocation & dispatch size to figure out how much to spill. The solution in this change is to make BROADCAST more like MOV_INDIRECT, so that you can do a BROADCAST(8) that actually reads a SIMD32 register. We put the size of the register read into src2. Now the spiller sees correct read/write sizes just looking at the destination register & dispatch size. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 662339a2ff ("brw/build: Use SIMD8 temporaries in emit_uniformize") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13614 Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36564>	2025-08-28 00:23:44 +03:00
Eric Engestrom	57484f6202	docs: add sha sum for 25.1.9 ... Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37031>	2025-08-27 19:23:18 +02:00
Eric Engestrom	8bd9e2a5ea	docs: add release notes for 25.1.9 ... Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37031>	2025-08-27 19:23:18 +02:00
Eric Engestrom	7525e77c52	docs: update calendar for 25.1.9 ... Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37031>	2025-08-27 19:23:18 +02:00
Aaron Ruby	c3533e49ab	gfxstream: Prune all guest-side KHR entrypoints that are provided with VK_VERSION_1_1 ... vk dispatch in mesa provides the redirection for this. Also, other recent changes have increment the minimium host requirement for gfxstream-vk to VK_VERSION_1_1, anyways. Reviewed-by: Gurchetan Singh <gurchetansingh@google.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36942>	2025-08-27 16:40:44 +00:00
Karol Herbst	4bce94e84b	nak: use logarithmic scaling in estimate_block_weight ... Instead of causing a +7000000% estimated cycles across a fossil-db run, this reduses that increase down to roughly +730%. With this a 6 level deep loop get's an estimated block weight of 385. The worst impacted shader gets its static cycle count increased by 240x, whish is 6 level deep and a huge loop body. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36528>	2025-08-27 15:39:04 +00:00
Karol Herbst	8cf91a4853	nak: protect static cycle counting against overflows ... Now with the loop aware cycle counting it's very likely that we'll overflow an u32 when counting, so do the counting in u64. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36528>	2025-08-27 15:39:04 +00:00
Lionel Landwerlin	e6ca709a4e	brw: fix INTEL_DEBUG=spill_fs ... We need to dirty the instruction BRW_DEPENDENCY_INSTRUCTIONS & BRW_DEPENDENCY_VARIABLES if anything was spilled. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: a6b0783375 ("brw: Use brw_ip_ranges in scheduling / regalloc") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13233 Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36925>	2025-08-27 15:08:35 +00:00
Mike Blumenkrantz	b122c3eaa9	zink: unify/fix clear flushing ... this ensures the blitting/queries_disabled flags are always set/unset and the layouts are too cc: mesa-stable Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37024>	2025-08-27 14:01:07 +00:00
Mike Blumenkrantz	c6062e8463	zink: update resized swapchain depth buffer layout while blitting ... this otherwise will not be set for the renderpass cc: mesa-stable Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37024>	2025-08-27 14:01:07 +00:00
Michal Krol	0aa5bed029	llvmpipe: Add support for 8x MSAA. ... Advertise format support for 8 samples. Extend tri rasteriser to operate on fb_max_samples samples, rather than hardcoded 4. Since we have run out of space for input mask in fragment shaders, add a second 64-bit input mask to handle samples 4 to 7. Add sample positions for 8xMSAA. Reviewed-by: Brian Paul brian.paul@broadcom.com Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37001>	2025-08-27 12:04:13 +00:00
Mike Blumenkrantz	92f2ef5a72	zink: fix sizing on resolve resource array ... let the compiler figure it out instead of mis-sizing it Fixes: a71b6ac41a ("tc: also inline depth resolves") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37012>	2025-08-27 11:12:13 +00:00
Mike Blumenkrantz	8c1519318f	zink: trigger fb unbind barrier on resolve images too ... these are likely to be used as fs textures, therefore always pre-sync them in tiler mode Fixes: a71b6ac41a ("tc: also inline depth resolves") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37012>	2025-08-27 11:12:13 +00:00
Christoph Pillmayer	5acedf5b31	pan/bi: Prioritize consts moved to the FAU ... Instead of allocating constants to the FAU entries on a first-come-first-serve basis, it would be more efficient to put the most frequently used constants in the FAU so we save the most amount of ADD_IMM to push constants into registers. This commit does so using a simple pass before the main constant lowering pass. Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36872>	2025-08-27 10:48:21 +00:00
Christoph Pillmayer	e83ca0e954	pan/va: Pull out constant swizzle handling ... Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36872>	2025-08-27 10:48:21 +00:00
Christoph Pillmayer	aa43ac4e7c	pan/bi: Move some constants into FAU entries ... Following on the previous commit, this commit adds support for selecting and reporting constants to pull from the FAU instead of loading them into registers first with ADD_IMM. This is beneficial because we can then use them as a source directly and save ourselves one instruction to move them into the register first. Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36872>	2025-08-27 10:48:20 +00:00
Christoph Pillmayer	12469ce821	panvk: Add support for moving constants to the FAU ... This commit sets up support for constants that should be pushed into FAU entries after the ones we already push (sysvals, push constants). The next commit will make the compiler actually find and report the constants that should be pushed. Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36872>	2025-08-27 10:48:19 +00:00
Georg Lehmann	acd879f096	radv: set ACCESS_CAN_SPECULATE for smem buffer loads with known good descriptors ... Foz-DB GFX1201: Totals from 2872 (3.59% of 80098) affected shaders: MaxWaves: 78208 -> 78234 (+0.03%); split: +0.21%, -0.18% Instrs: 6214171 -> 6193701 (-0.33%); split: -0.40%, +0.07% CodeSize: 33121244 -> 33113692 (-0.02%); split: -0.18%, +0.16% VGPRs: 151680 -> 152016 (+0.22%); split: -0.25%, +0.47% SpillSGPRs: 775 -> 776 (+0.13%) Latency: 46080905 -> 45955331 (-0.27%); split: -0.55%, +0.28% InvThroughput: 6235954 -> 6250598 (+0.23%); split: -0.25%, +0.48% VClause: 111125 -> 110955 (-0.15%); split: -0.17%, +0.02% SClause: 221845 -> 214761 (-3.19%); split: -3.20%, +0.01% Copies: 501387 -> 488215 (-2.63%); split: -2.96%, +0.33% Branches: 191455 -> 178574 (-6.73%) PreSGPRs: 146364 -> 146923 (+0.38%); split: -0.12%, +0.50% PreVGPRs: 120813 -> 121073 (+0.22%) VALU: 3139282 -> 3137471 (-0.06%); split: -0.11%, +0.05% SALU: 1079863 -> 1083158 (+0.31%); split: -0.55%, +0.86% VMEM: 182255 -> 182247 (-0.00%) SMEM: 293409 -> 290233 (-1.08%) Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36938>	2025-08-27 09:45:19 +00:00
Georg Lehmann	3b06824e4c	nir/opt_algebraic: optimize some post peephole select patterns ... Foz-DB GFX1201: Totals from 208 (0.26% of 80287) affected shaders: Instrs: 427684 -> 426834 (-0.20%); split: -0.22%, +0.02% CodeSize: 2232616 -> 2228816 (-0.17%); split: -0.20%, +0.03% Latency: 3993934 -> 3992726 (-0.03%); split: -0.04%, +0.01% InvThroughput: 569055 -> 568622 (-0.08%); split: -0.09%, +0.01% SClause: 12932 -> 12927 (-0.04%) Copies: 22567 -> 22604 (+0.16%); split: -0.47%, +0.63% Branches: 7671 -> 7658 (-0.17%) VALU: 222047 -> 221625 (-0.19%) SALU: 83954 -> 83815 (-0.17%); split: -0.29%, +0.13% Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36938>	2025-08-27 09:45:19 +00:00
Georg Lehmann	395893e16b	nir/peephole_select: allows more lowered io ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36938>	2025-08-27 09:45:19 +00:00
Samuel Pitoiset	81142f4574	radv: add radv_cmd_set_color_blend_equation() ... Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36979>	2025-08-27 09:22:43 +00:00
Samuel Pitoiset	7a196d05a3	radv: add radv_cmd_set_sample_locations() ... Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36979>	2025-08-27 09:22:43 +00:00
Samuel Pitoiset	62574e956c	radv: add radv_cmd_set_rendering_input_attachment_indices() ... Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36979>	2025-08-27 09:22:42 +00:00
Samuel Pitoiset	64daa52e9c	radv: add radv_cmd_set_rendering_attachment_locations() ... Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36979>	2025-08-27 09:22:42 +00:00
Samuel Pitoiset	0975d0ace9	radv: add radv_cmd_set_color_blend_enable() ... Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36979>	2025-08-27 09:22:41 +00:00
Samuel Pitoiset	ea3bfcf29f	radv: pre-compute color blend enable ... Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36979>	2025-08-27 09:22:41 +00:00
Samuel Pitoiset	73f7253a70	radv: make radv_ps_epilog_state::color_blend_enable a 8-bit field ... Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36979>	2025-08-27 09:22:40 +00:00