Commit graph

133309 commits

Author SHA1 Message Date
Mike Blumenkrantz
34f0aef19b radv: just use UINT64_MAX when getting absolute timeout for that value
this would otherwise result in (UINT64_MAX - gettime()), which can effectively
be rounded to UINT64_MAX without a noticeable change

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12680>
2021-09-01 17:47:33 +00:00
Mike Blumenkrantz
45f35900c3 mesa/st: create new surfaces before destroying old ones when updating attachments
try to avoid patterns that would destroy surfaces for drivers that cache them for
deduplication purposes

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12651>
2021-09-01 15:43:48 +00:00
Adrian Bunk
7155676618 util/format: NEON is not available with the soft-float ABI
Fixes: 80923e8d58 ("util/format: Add some NEON intrinsics-based u_format_unpack.")
Reviewed-by: Emma Anholt <emma@anholt.net>
Tested-by: Ross Burton <ross.burton@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12569>
2021-09-01 15:18:02 +00:00
Timur Kristóf
fe6e4484ab ac/nir/nggc: Move gs_alloc_req up in NGG culling shaders.
This is the first part of a refactor to make vertex compaction optional.
Additionally, it may yield a very small benefit to allocate the PC
space sligtly sooner.

Fossil DB stats on Sienna Cichlid with NGGC on:

Totals from 58239 (45.27% of 128647) affected shaders:
CodeSize: 160502348 -> 160502340 (-0.00%)
Instrs: 30722664 -> 30722662 (-0.00%)
Latency: 137627419 -> 137782218 (+0.11%); split: -0.00%, +0.11%
InvThroughput: 21698587 -> 21699068 (+0.00%); split: -0.00%, +0.00%
Copies: 3288263 -> 3288261 (-0.00%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12246>
2021-09-01 14:45:14 +00:00
Timur Kristóf
f4a65e5628 ac/nir/nggc: Only repack arguments that are needed.
Don't repack everything, only what is actually used.
The goal of this commit is primarily to remove unnecessary
LDS stores and loads. In addition to that, it also gets rid of
a few VALU instructions and reduces VGPR use.

Fossil DB stats on Sienna Cichlid with NGGC on:

Totals from 6951 (5.40% of 128647) affected shaders:
VGPRs: 206056 -> 205360 (-0.34%); split: -0.79%, +0.45%
CodeSize: 12344568 -> 12269312 (-0.61%); split: -0.62%, +0.01%
MaxWaves: 211206 -> 212196 (+0.47%)
Instrs: 2319459 -> 2308483 (-0.47%); split: -0.50%, +0.03%
Latency: 7220829 -> 7164721 (-0.78%); split: -1.21%, +0.43%
InvThroughput: 1051450 -> 1049191 (-0.21%); split: -0.36%, +0.15%
VClause: 25794 -> 25445 (-1.35%); split: -1.97%, +0.61%
SClause: 39192 -> 39277 (+0.22%); split: -0.21%, +0.43%
Copies: 315756 -> 313404 (-0.74%); split: -1.17%, +0.42%
Branches: 127878 -> 127879 (+0.00%); split: -0.00%, +0.00%
PreVGPRs: 168029 -> 160162 (-4.68%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12246>
2021-09-01 14:45:14 +00:00
Timur Kristóf
02bba6aab5 ac/nir/nggc: Don't stop applying reusable variables at prim export.
This was a mistake that prevented reusing variables in shaders
with late primitive export.

Fossil DB stats on Sienna Cichlid with NGGC on:

Totals from 6547 (5.09% of 128647) affected shaders:
VGPRs: 323368 -> 323824 (+0.14%); split: -0.03%, +0.18%
SpillSGPRs: 45 -> 4865 (+10711.11%)
CodeSize: 34208732 -> 33855952 (-1.03%); split: -1.21%, +0.18%
MaxWaves: 142538 -> 142456 (-0.06%); split: +0.04%, -0.09%
Instrs: 6654252 -> 6606432 (-0.72%); split: -0.89%, +0.17%
Latency: 30527770 -> 30452769 (-0.25%); split: -0.42%, +0.18%
InvThroughput: 5604540 -> 5609450 (+0.09%); split: -0.04%, +0.13%
VClause: 121531 -> 120448 (-0.89%); split: -1.17%, +0.27%
SClause: 195388 -> 177902 (-8.95%); split: -9.14%, +0.19%
Copies: 617949 -> 636397 (+2.99%); split: -0.44%, +3.42%
Branches: 228184 -> 228281 (+0.04%); split: -0.09%, +0.13%
PreSGPRs: 271395 -> 343555 (+26.59%); split: -0.01%, +26.60%
PreVGPRs: 277650 -> 277710 (+0.02%); split: -0.01%, +0.03%

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12246>
2021-09-01 14:45:14 +00:00
Timur Kristóf
59de9620b4 ac/nir/ngg: Delete unused struct.
This was left there by accident after a rebase mistake.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12246>
2021-09-01 14:45:14 +00:00
Tomeu Vizoso
25720f84df lavapipe: Use c_msvc_compat_args
So local builds fail before the Windows build finds out.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12662>
2021-09-01 16:00:01 +02:00
Danylo Piliaiev
6373dd814a ir3/a6xx,freedreno: account for resinfo return size dependency on IBO_0_FMT
On a6xx resinfo returns size in bytes divided by IBO_0_FMT format size
(not just size in dwords), we have to shift it back to NIR meaning which
is size in bytes.

Make freedreno use 16b buffers when they are supported in order to be
able to depend on hardware capabilities when lowering ssbo size.

Fixes: ce1a381e57 "turnip: enable VK_KHR_16bit_storage on A650"

Fixes cts tests:
    dEQP-VK.ssbo.unsized_array_length.float_offset_explicit_size
    dEQP-VK.ssbo.unsized_array_length.float_no_offset_whole_size
    dEQP-VK.compute.basic.write_multiple_unsized_arr_single_invocation
and many more

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12485>
2021-09-01 16:09:20 +03:00
Mykhailo Skorokhodov
e8cbfa95a3 iris: Fix compute shader leak
Variant after creation with the function iris_create_shader_variant
requires to be added to variants. Otherwise there is a memory
leak after execution.

Fixes: 2024d470483("iris: Add the variant to the list as early as possible")
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12645>
2021-09-01 10:02:38 +00:00
Timur Kristóf
9d20cf2732 aco: Fix invalid usage of std::fill with std::array.
In this case std::array doesn't behave like a regular array, therefore
it is NOT okay to index it outside the array, even though std::fill
needs us to do so.

Change the syntax to do the same thing slightly differently,
and add an assertion to make sure the registers are always within
the array's bounds.

Closes: #5289
Fixes: 0e4747d3fb
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12664>
2021-09-01 09:33:28 +00:00
Vinson Lee
498d93f3dd glx: Fix unused-variable warning with macOS build.
../src/glx/tests/indirect_api.cpp:52:20: warning: unused variable 'nil' [-Wunused-variable]
static const void *nil = 0;
                   ^

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12607>
2021-09-01 09:03:53 +00:00
Timur Kristóf
33630090a2 nir: Add comment to explain the sad_u8x4 opcode.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12649>
2021-09-01 08:42:03 +00:00
Connor Abbott
77a852c1ba lima/gpir: Rewrite register allocation for value registers
The usual linear-scan register allocation algorithm can't handle
preallocated registers, since we might be forced to choose a color for
a non-preallocated variable that overlaps with a pre-allocated variable.
But in such cases we can simply split the live range of the offending
variable when we reach the beginning of the pre-allocated variable's
live range. This is still optimal in the sense that it always finds a
coloring whenever one is possible, but we may not insert the smallest
possible number of moves. However, since it's actually the scheduler
which splits live ranges afterwards, we can simply fold in the move
while keeping its fake dependencies, and then everything still works! In
other words, inserting a live range split for a value register during
register allocation is pretty much free.

This means that we can split register allocation in two. First globally
allocate the cross-block registers accessed through load_reg and
store_reg instructions, which is still done via graph coloring, and then
run a linear scan algorithm over each block, treating the load_reg and
store_reg nodes as referring to pre-allocated registers. This makes the
existing RA more complicated, but it has two benefits: first, using
round-robin with the linear scan allocator results in much fewer fake
dependencies, resulting in around 15 less instructions in the glmark2
jellyfish shader and fixing a regression in instruction count since
branching support went in. Second, it will simplify handling spilling.
With just graph coloring for everything, every time we spill a node, we
have to create new value registers which become new nodes in the graph
and re-run RA. This is worsened by the fact that when writing a value to
a temporary, we need to have an extra register available to load the
write address with a load_const node. With the new scheme, we can ignore
this entirely in the first part and then in the second part we can just
reserve an extra register in sections where we know we have to spill. So
no re-running RA many times, and we can get a good result quickly.

The current implementation does linear scan backwards, so that we can
insert the fake dependencies while allocating and avoid creating any
move nodes at all when we have to split a live range. However, it turns
out that this makes handling schedule_first nodes a bit more
complicated, so it's not clear if that was worth it.

Note:
The commit was originally authored by Connor Abbott <cwabbott@gmail.com>
and was cherry-picked from <mesa/mesa!2315>.
Rebasing was necessary due to changes to BITSET_FOREACH_SET,
see 4413537c
Because some deqp tests pass now, deqp-lima-fails.txt was also changed.
The above changes are

Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7682>
2021-09-01 08:30:57 +00:00
Connor Abbott
3d957b40cc lima: Add a NIR load duplicating pass
and use it with vertex shaders.

Note:
The commit was originally authored by Connor Abbott <cwabbott@gmail.com>
and was cherry-picked from <mesa/mesa!2315>.
Apart from some changes, which were necessary due to rebasing, the following
changes have been added:
clone_intrinsic() was changed to use nir_instr_clone() instead of
doing it manually.
Tests against `src->parent_instr->type != nir_instr_type_phi` have been
inserted, otherwise we may run into a nir validation error.
Intrinsic load_input and load_uniform  are not duplicated, if their source
type is nir_instr_type_load_const.
The above changes are

Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7682>
2021-09-01 08:30:57 +00:00
Marek Olšák
ef190b9e15 radeonsi: clean up typecasts in compute_copy_image
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449>
2021-09-01 07:51:30 +00:00
Marek Olšák
34a2c75310 radeonsi: enable DCC stores on gfx10.3 APUs for better performance
There is just one hw bug that we need to handle.

NO_DCC_FB was unused.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449>
2021-09-01 07:51:30 +00:00
Marek Olšák
c88a546550 radeonsi: track displayable_dcc_dirty for non-compute shaders
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449>
2021-09-01 07:51:30 +00:00
Marek Olšák
8c845d4cb4 radeonsi: rename DCC_WRITE -> ALLOW_DCC_STORE
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449>
2021-09-01 07:51:30 +00:00
Marek Olšák
550f859c53 radeonsi: handle pipe_aligned in compute_expand_fmask
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449>
2021-09-01 07:51:30 +00:00
Marek Olšák
0c39597734 radeonsi: add missing make_CB_shader_coherent for DCC stores into copy_image
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449>
2021-09-01 07:51:30 +00:00
Marek Olšák
cb845c53f4 radeonsi: enable DCC stores for clear_render_target on gfx10
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449>
2021-09-01 07:51:30 +00:00
Marek Olšák
b648d6fbf8 radeonsi: disable DCC stores on Navi12-14 for displayable DCC to fix corruption
This is a hardware limitation.

Fixes: 1d64a1045e "radeonsi: enable dcc image stores on gfx10+"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12449>
2021-09-01 07:51:30 +00:00
Mike Blumenkrantz
0b2b2a4783 zink: remove ZINK_HEAP_HOST_VISIBLE_ANY
this was just the coherent heap but splitting the slabs more to make
suballocating worse

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12659>
2021-09-01 04:24:03 +00:00
Mike Blumenkrantz
a923835afc zink: clamp lazy pools to 500 descriptors and allocate more slowly
now that these can get popped without stalling, they can be much smaller
to avoid exploding available memory or address space

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12658>
2021-09-01 04:13:07 +00:00
Mike Blumenkrantz
70f1337f63 zink: use compatible renderpass state in pipeline hash
this massively deduplicates the number of pipelines

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12605>
2021-09-01 03:28:11 +00:00
Mike Blumenkrantz
8dac288c8d zink: track compatible render passes
Two render passes are compatible if their corresponding color, input, resolve, and depth/stencil
attachment references are compatible and if they are otherwise identical except for:
• Initial and final image layout in attachment descriptions
• Load and store operations in attachment descriptions
• Image layout in attachment references

VK 8.2

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12605>
2021-09-01 03:28:11 +00:00
Mike Blumenkrantz
d7e36a1831 zink: inline gfx pipeline hash table
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12605>
2021-09-01 03:28:11 +00:00
Mike Blumenkrantz
15450d2c2e zink: incrementally hash all pipeline component hashes
not the actual pipeline hash, just the components

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12605>
2021-09-01 03:28:11 +00:00
Mike Blumenkrantz
12cf0099fd zink: incrementally hash vertex state into pipeline hash
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12605>
2021-09-01 03:28:11 +00:00
Mike Blumenkrantz
6fd5565933 zink: incrementally hash module variants in pipeline
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12605>
2021-09-01 03:28:11 +00:00
Mike Blumenkrantz
7f23c9daca zink: incrementally hash gfx shader stages
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12605>
2021-09-01 03:28:11 +00:00
Mike Blumenkrantz
07240424ca zink: don't use dynamic vertex stride with dynamic vertex input
avoid spurious validation errors and potential driver fails from updating
stride twice

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12604>
2021-09-01 03:18:14 +00:00
Mike Blumenkrantz
34abd8761a zink: dynamic vertex input template
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12604>
2021-09-01 03:18:14 +00:00
Mike Blumenkrantz
e53e5165b1 zink: create inner scanout object without scanout binds
this restores mutable formats to the inner object to work with scanout

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12629>
2021-09-01 03:07:55 +00:00
Mike Blumenkrantz
63e62af31c zink: ensure gfx shader module states are updated when doing a partial recalc
these are in the pipeline state and must be updated

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12632>
2021-09-01 02:56:04 +00:00
Mike Blumenkrantz
c71e662ae2 zink: remove refcounting from batch states
these are always destroyed by the context, no exceptions

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12633>
2021-09-01 02:46:00 +00:00
Mike Blumenkrantz
39df394ffe zink: split out stalling from fence-waiting function
stall and flush+stall are not the same; in some cases, the driver must only
stall and never flush, so ensure that this is possible to avoid infinite
recursion

fixes Metro Last Light: Redux benchmark mode

Fixes: d8905446d6 ("zink: rework oom flushing")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12652>
2021-09-01 02:35:38 +00:00
Mike Blumenkrantz
2aaca02bbf zink: use tc rebind info for buffer replacements
this makes the most common type of replacement more efficient

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12575>
2021-09-01 02:23:05 +00:00
Mike Blumenkrantz
52a846d147 zink: directly pass resource pointer to descriptor state updates
this should cut down a little more overhead

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12575>
2021-09-01 02:23:05 +00:00
Mike Blumenkrantz
802e43a6b5 gallium/cso: add unbind mask for cso restore
this code was duplicated in a bunch of places, so now there can just
be a bitmask passed to simplify and consolidate

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12571>
2021-09-01 01:59:52 +00:00
Mike Blumenkrantz
7ac2edd555 aux/cso: always restore states in atom order
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12571>
2021-09-01 01:59:52 +00:00
Mike Blumenkrantz
b7534fe82a zink: destroy shader modules on program free to avoid leaking
it's irrelevant whether the shader pointer is valid, the shader cache
may still exist

Fixes: a92442225c ("zink: split up shader cache per-stage")

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12650>
2021-09-01 01:48:04 +00:00
Tomeu Vizoso
eb7eccc76f lavapipe: Use generated command queue code
Most of the code that implements entry points for commands doesn't need
to be manually written. So just drop it.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12369>
2021-09-01 01:05:22 +00:00
Tomeu Vizoso
997a6ca226 vulkan: Generate entrypoints that enqueue commands
For drivers such as Lavapipe that record the commands at the execution
stage.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12369>
2021-09-01 01:05:22 +00:00
Tomeu Vizoso
a7b0946ef0 vulkan: Generate code to place commands in a queue
It can be used by lavapipe and also by drivers for GPUs with command
streams that require values related to the framebuffer, thus the command
stream emission for secondary buffers needs to be deferred until the
framebuffer is known (execution time).

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12369>
2021-09-01 01:05:22 +00:00
Tomeu Vizoso
925a8fac17 vulkan: Read len attribute of parameters to functions
It will be needed for generating code that needs to know the size of
arrays.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12369>
2021-09-01 01:05:22 +00:00
Tomeu Vizoso
77ad17d022 lavapipe: add xfails for whole of CTS
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12369>
2021-09-01 01:05:22 +00:00
Marek Olšák
3362da2c53 ac/gpu_info: fix detection of smart access memory
chip_class was 0. Move the code after setting chip_class.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5282

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>
2021-09-01 00:42:58 +00:00
Marek Olšák
e05ad2680c radeonsi: set gfx10 registers better in si_emit_initial_compute_regs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>
2021-09-01 00:42:58 +00:00