Commit graph

112250 commits

Author SHA1 Message Date
Kenneth Graunke
340df53d6a iris: Fix resource tracking for CS thread ID buffer
Today, we stream the compute shader thread IDs simply because they're
(annoyingly) relative to dynamic state base address.  We could upload
them once at compile time, but we'd need a separate non-streaming
uploader for IRIS_MEMZONE_DYNAMIC, and I'm not sure it's worth it.

stream_state pins the buffer for use in the current batch, but also
returns a reference to the pipe_resource.  We dropped this reference
on the floor, leaking a reference basically every time we dispatched
a compute shader after switching to a new one.

The reason it returns a reference is so that we can hold on to it and
re-pin it in iris_restore_compute_saved_bos, which we were also failing
to do.  So if we actually filled up a batch with repeated dispatches to
the same compute shader, and flushed, then continued dispatching, we
would fail to pin it and likely GPU hang.
2019-06-27 08:12:22 -07:00
Kenneth Graunke
16d334951e iris: Only bother with thread ID upload if doing MEDIA_CURBE_LOAD
We were unconditionally uploading the new data, but then conditionally
using it with MEDIA_CURBE_LOAD.  If we're not going to emit the command,
there's no point in uploading the data.
2019-06-27 08:12:22 -07:00
Kenneth Graunke
8f51f1ba6e iris: Do MEDIA_CURBE_LOAD when IRIS_DIRTY_CS is set, not constants
We only use push the compute shader thread IDs, not any actual constant
buffer data.  So we should track the compute shader variant changing,
not constbuf changes.
2019-06-27 08:12:22 -07:00
Kenneth Graunke
85c72da1b1 iris: Drop UBO range stuff from iris_restore_compute_saved_bos
Compute doesn't use UBO ranges (annoyingly), so this is dead code.
2019-06-27 08:12:22 -07:00
Kenneth Graunke
f94ebf0c9d iris: Properly align interface descriptor data addresses
MEDIA_INTERFACE_DESCRIPTOR's Interface Descriptor Data Start Address
field's docs say: "This bit specifies the 64-byte aligned address..."

And we were doing 32.  Superfluous thread ID uploading was apparently
saving us from GPU hangs in most cases.
2019-06-27 08:12:22 -07:00
Andrii Simiklit
62c6059584 mesa: use a correct function return type
v2: standard 'bool' can be used
     ( Eric Engestrom <eric.engestrom@intel.com> )

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
2019-06-27 07:53:41 +00:00
Tomeu Vizoso
9bef1f1ff1 panfrost/decode: Mention the address of a few descriptors
When the fault_pointer field in the header is set, we can get some idea
of which descriptor the HW isn't happy with if we know their addresses.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-27 09:13:48 +02:00
Tomeu Vizoso
de02fb19ed panfrost/decode: Wait for a job to finish before dumping
Then we can get some information back about any exception that might
have happened.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-27 09:13:42 +02:00
Tomeu Vizoso
fa36c194fd panfrost/decode: Decode exception status
Arm's kernel driver mentions how to decode this field, which makes a bit
clearer what had happened.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-27 09:13:35 +02:00
Tomeu Vizoso
b26c2b4840 panfrost/decode: Print AFBC struct when appropriate
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-27 09:12:56 +02:00
Samuel Pitoiset
d5004f60be radv: only export clip/cull distances if PS reads them
The only exception is the GS copy shader which emits them
unconditionally.

Totals from affected shaders:
SGPRS: 71320 -> 71008 (-0.44 %)
VGPRS: 54372 -> 54240 (-0.24 %)
Code Size: 2952628 -> 2941368 (-0.38 %) bytes
Max Waves: 9689 -> 9723 (0.35 %)

This helps Dota2, Doom, GTAV and Hitman 2.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-27 08:56:37 +02:00
Samuel Pitoiset
1e9ccc5429 radv: fix FMASK expand if layerCount is VK_REMAINING_ARRAY_LAYERS
This doesn't fix anything known, but it's likely going to
break if layerCount is ~0U.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-27 08:56:34 +02:00
Kenneth Graunke
8551dc17a7 iris: Disable loop unrolling in GLSL IR.
Leave it to NIR instead, like i965 does.  Thanks to Tim Arceri for
noticing that I'd left this enabled by accident.

shader-db results on Skylake:

total instructions in shared programs: 15522628 -> 15521642 (<.01%)
instructions in affected programs: 94008 -> 93022 (-1.05%)
helped: 34
HURT: 33
helped stats (abs) min: 12 max: 48 x̄: 33.82 x̃: 42
helped stats (rel) min: 0.06% max: 22.14% x̄: 9.86% x̃: 10.89%
HURT stats (abs)   min: 1 max: 16 x̄: 4.97 x̃: 3t
HURT stats (rel)   min: 0.82% max: 3.77% x̄: 1.73% x̃: 1.53%
95% mean confidence interval for instructions value: -20.08 -9.35
95% mean confidence interval for instructions %-change: -5.95% -2.36%
Instructions are helped.

total cycles in shared programs: 367105221 -> 367074230 (<.01%)
cycles in affected programs: 10017660 -> 9986669 (-0.31%)
helped: 266
HURT: 184
helped stats (abs) min: 1 max: 9556 x̄: 151.35 x̃: 12
helped stats (rel) min: 0.08% max: 59.91% x̄: 4.66% x̃: 1.67%
HURT stats (abs)   min: 1 max: 1716 x̄: 50.37 x̃: 6
HURT stats (rel)   min: <.01% max: 24.40% x̄: 2.42% x̃: 0.85%
95% mean confidence interval for cycles value: -133.90 -3.84
95% mean confidence interval for cycles %-change: -2.44% -1.10%
Cycles are helped.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-06-26 22:55:03 -07:00
Kenneth Graunke
acadeaff6a st/mesa: Set EmitNoIndirectSampler if GLSLVersion < 400.
This patch changes the code which sets EmitNoIndirectSampler to check
the core profile GLSL version, rather than the ARB_gpu_shader5 extension
enable.  st/mesa exposes ARB_gpu_shader5 if GLSLVersion (in core
profiles) or GLSLVersionCompat (in compat profiles) >= 400.

The Intel drivers do not currently expose ARB_gpu_shader5 in compat
profiles.  But the backend can absolutely handle indirect samplers.
Looking at the core profile version number should be a good indication
of what the driver supports.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-06-26 22:54:52 -07:00
Kenneth Graunke
116144d65e iris: Delete dead ice->state.streamout_strides field.
Nothing uses this, it must be a remnant from an earlier approach.
2019-06-26 20:17:22 -07:00
Caio Marcelo de Oliveira Filho
085c0f1f13 nir/algebraic: Add helpers and a rule involving wrapping
The helpers are needed so we can use the syntax `instr(cond)` in the
algebraic rules.  Add simple rule for dropping a pair of mul-div of
the same value when wrapping is guaranteed to not happen.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-06-26 14:13:02 -07:00
Caio Marcelo de Oliveira Filho
5a143965b8 spirv: Implement NoSignedWrap and NoUnsignedWrap decorations
When handling the specified ALU operations, check for the decorations
and set nir_alu_instr no_signed_wrap and no_unsigned_wrap flags accordingly.

v2: Add a glsl_base_type_is_unsigned_integer() helper.  (Karol)

v3: Rename helper to glsl_base_type_is_uint().

v4: Use two flags, so we don't need the helper anymore.  (Connor)

v5: Pass alu directly to handle function.  (Jason)

Reviewed-by: Karol Herbst <kherbst@redhat.com> [v3]
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-06-26 14:13:02 -07:00
Caio Marcelo de Oliveira Filho
ae37237713 nir: Add a no wrapping bits to nir_alu_instr
They indicate the operation does not cause overflow or underflow.
This is motivated by SPIR-V decorations NoSignedWrap and
NoUnsignedWrap.

Change the storage of `exact` to be a single bit, so they pack
together.

v2: Handle no_wrap in nir_instr_set.  (Karol)

v3: Use two separate flags, since the NIR SSA values and certain
    instructions are typeless, so just no_wrap would be insufficient
    to know which one was referred to.  (Connor)

v4: Don't use nir_instr_set to propagate the flags, unlike `exact`,
    consider the instructions different if the flags have different
    values.  Fix hashing/comparing.  (Jason)

Reviewed-by: Karol Herbst <kherbst@redhat.com> [v1]
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-06-26 14:13:02 -07:00
Dylan Baker
f97dcb7a55 docs: add news item and link release notes for 19.0.8
This is an emergency release due to a critical bug.
2019-06-26 13:48:06 -07:00
Dylan Baker
290495a431 docs: Add mesa 19.0.8 sha256 sums 2019-06-26 13:46:30 -07:00
Dylan Baker
10a24925a0 docs: Add docs for 19.0.8 2019-06-26 13:46:29 -07:00
Jonathan Marek
a70ff70158 nir: remove fnot/fxor/fand/for opcodes
There doesn't seem to be any reason to keep these opcodes around:
* fnot/fxor are not used at all.
* fand/for are only used in lower_alu_to_scalar, but easily replaced

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-06-26 15:26:10 -04:00
Jonathan Marek
0b5a483baa nir: opt_vectorize: combine different constant sources
We can vectorize instructions with different constant sources by creating
a new load_const and using that.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-26 14:56:28 -04:00
Alyssa Rosenzweig
10688257bd panfrost/midgard: Merge embedded constants
In Midgard, a bundle consists of a few ALU instructions. Within the
bundle, there is room for an optional 128-bit constant; this constant is
shared across all instructions in the bundle.

Unfortunately, many instructions want a 128-bit constant all to
themselves (how selfish!). If we run out of space for constants in a
bundle, the bundle has to be broken up, incurring a performance and
space penalty.

As an optimization, the scheduler now analyzes the constants coming in
per-instruction and attempts to merge shared components, adjusting the
swizzle accessing the bundle's constants appropriately. Concretely,
given the GLSL:

   (a * vec4(1.5, 0.5, 0.5, 1.0)) + vec4(1.0, 2.3, 2.3, 0.5)

instead of compiling to the naive two bundles:

   vmul.fmul [temp], [a], r26
   fconstants 1.5, 0.5, 0.5, 1.0

   vadd.fadd [out], [temp], r26
   fconstants 1.0, 2.3, 2.3, 0.5

The scheduler can now fuse into a single (pipelined!) bundle:

   vmul.fmul [temp], [a], r26.xyyz
   vadd.fadd [out], [temp], r26.zwwy
   fconstants 1.5, 0.5, 1.0, 2.3

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-26 10:01:36 -07:00
Alyssa Rosenzweig
a0a34946d8 panfrost/midgard: Share swizzle compose
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-26 10:01:36 -07:00
Alyssa Rosenzweig
f6fde45d5c panfrost/midgard: Share swizzle/mask code
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-26 10:01:36 -07:00
Alyssa Rosenzweig
0979ea9de8 panfrost: Fix checksumming typo
Fixes: 3e6c6bb0 ("panfrost: Merge checksum buffer with main BO")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-26 09:58:30 -07:00
Kenneth Graunke
ab009b7d6e iris: Fix overzealous query object batch flushing.
In the past, each query object had their own BO.  Checking if the batch
referenced that BO was an easy way to check if commands were still
queued to compute the query value.  If so, we needed to flush.

More recently (c24a574e6c), we started using an u_upload_mgr for query
objects, placing multiple queries in the same BO.  One side-effect is
that iris_batch_references is a no longer a reasonable way to check if
commands are still queued for our query.  Ours might be done, but a
later query that happens to be in the same BO might be queued.  We don't
want to flush in that case.

Instead, check if the current batch's signalling syncpt is the one we
referenced when ending the query.  We know the syncpt can't have been
reused because our query is holding a reference, so a simple pointer
comparison should suffice.

Removes all batch flushing caused by query objects in Shadow of Mordor.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2019-06-26 09:49:01 -07:00
Kenneth Graunke
db878a728c iris: Make an iris_batch_get_signal_syncpt() helper.
This returns a pointer to the signalling syncpt, without incrementing
the reference count.  This can be useful for comparisons.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2019-06-26 09:49:01 -07:00
Boris Brezillon
443e530194 panfrost: Remove unneeded check in panfrost_scissor_culls_everything()
The ss local var is guaranteed to be != NULL. Get rid of this useless
check.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-26 09:35:25 -07:00
Alyssa Rosenzweig
d4575c3071 panfrost: Update copyright identifiers
"Collabora, Ltd." should be listed in lieu of simply "Collabora"

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Suggested-by: Daniel Stone <daniels@collabora.com>
2019-06-26 09:10:51 -07:00
Alyssa Rosenzweig
b0e8941df1 panfrost/midgard: Reorder to permit constant bias
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-26 09:08:37 -07:00
Alyssa Rosenzweig
213b62810d panfrost/midgard: Add helper to encode constant bias
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-26 09:08:37 -07:00
Alyssa Rosenzweig
b51727ea28 panfrost/midgard: Handle negative immediate bias
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-26 09:08:37 -07:00
Rob Clark
1833827eac freedreno: correct batch_depends_on() logic
Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-06-26 08:43:02 -07:00
Rob Clark
2b10bb6e5e freedreno: drop unused arg from fd_batch_flush()
The `force` arg has been unused for a while.. but apparently I forgot to
garbage collect it.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-06-26 08:43:02 -07:00
Timothy Arceri
5f809e2707 st/glsl: fix silly regression finding gs/tes variants
Fixes: d19fe5e67a ("st/glsl: support clamping color outputs in compat for gs/tes")

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2019-06-26 23:13:02 +10:00
Timothy Arceri
d19fe5e67a st/glsl: support clamping color outputs in compat for gs/tes
This support requires the driver to be a NIR driver as we use the
NIR lowering pass to do the clamping.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-06-26 00:36:48 +00:00
Timothy Arceri
f5f31612d3 nir: add tess support to nir_lower_clamp_color_outputs()
This will be used to add compat profile support for higher GL
versions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-06-26 00:36:48 +00:00
Sagar Ghuge
06807e1948 glsl: Fix round64 conversion function
Fix round64 function to handle round to nearest even cases specially
with positive and negative numbers with fraction part 0.5.

v2: 1) Simplify unused bits (Elie Tournier)

Fixes:
   KHR-GL45.gpu_shader_fp64.builtin.round_dvec2
   KHR-GL45.gpu_shader_fp64.builtin.round_dvec3
   KHR-GL45.gpu_shader_fp64.builtin.round_dvec4
   KHR-GL45.gpu_shader_fp64.builtin.roundeven_double
   KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec2
   KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec3
   KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec4

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2019-06-25 15:19:10 -07:00
Alyssa Rosenzweig
e8f4c9f56c panfrost/ci: Add RK3288 flipflops I don't want to deal with right now
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:42:58 -07:00
Alyssa Rosenzweig
70a87a915d panfrost/ci: Update failures list
A ton of tests were fixed by this series. A few were incorrectly passing
before (QualityError, for instance) and now are explicitly failing. A
few legitimate regressions but overwhelmingly positive.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:18 -07:00
Alyssa Rosenzweig
ddf5f04edf panfrost/ci: Set MESA_GLES_VERSION_OVERRIDE=3.0
Fixes cube map tests due to disagreements between Mesa, dEQP, and the
spec...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-06-25 13:39:18 -07:00
Alyssa Rosenzweig
33f3cac1c2 panfrost/ci: Run full set of mipmap tests
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:18 -07:00
Alyssa Rosenzweig
f34635c699 panfrost: Advertise support for other 8-bit UNORM formats
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:18 -07:00
Alyssa Rosenzweig
310ca6ba40 panfrost: Use pipe_surface->format directly in blitter
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:18 -07:00
Alyssa Rosenzweig
5cfb4248c6 panfrost: Invert swizzle for rendering
Fixes rendering to e.g. alpha textures.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:18 -07:00
Alyssa Rosenzweig
b96f119d85 panfrost: Honour first_layer...last_layer when sampling
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:18 -07:00
Alyssa Rosenzweig
0ad17f56ae panfrost: Use the sampler_view target (not the textures)
u_blitter gets "special treatment" and uses this mechanism to cast
cube maps to 2D textures in order to texelFetch them.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:18 -07:00
Alyssa Rosenzweig
faf8ad4875 panfrost/midgard: Assert guard texelFetch against cubemaps
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-25 13:39:18 -07:00