Enabling DS resolve attachment entails a blit for a ZLS subtile region, in such
case the TQ needs to know the number of samples in the source surface in order to
pack the texture state.
Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37512>
This commit enables the VK_KHR_depth_stencil_resolve extension in the PVR
Vulkan driver. Only worth to note that this implementation is based on the
renderpass driver path and it will need a rework as part of the dynamic
rendering enablement.
Signed-off-by: leonperianu <leon.perianu@imgtec.com>
Co-authored-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Co-authored-by: Ashish Chauhan <ashish.chauhan@imgtec.com>
Co-authored-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37512>
Do not conflate api and internal driver use of copy commands and make the
correct assumptions for the api path, according to the Vulkan spec.
Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37512>
The driver already implements the regular render pass functions in terms of the
VK_KHR_create_renderpass2 functions. However, the extension couldn't be
advertised due to missing support for VK_KHR_multiview. Now multiview is
supported, renderpass2 can be advertised as well.
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37512>
- Pass view index to fragment shader via linked flat varying.
- Use view index instead of layer id for input attachments when required.
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37512>
- Fix ds address offset for multiview.
- Fix multiview depth/stencil address by restoring it after every kick.
- Enable empty tile processing after first subpass for multiview.
Signed-off-by: Peter Quayle <peter.quayle@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37512>
Sets up the PDS doutu sample rate as late as possible, utilises
covmask(1.0f) to detect whether the fragment shader is running in single
sampled mode or not in order to select registers that differ based on
the execution rate.
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37512>
Xe2 platforms have a different way to disable CCS
compression.
Suggested by Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37098>
This helps us to catch a compressed bo is picked up for
an uncompressed modifiers when importing dmabuf, and vise
versa.
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37098>
For an image created either without a modifier to share or as the
destination image to get rid of compression by re-allocation, it
should have compression disabled.
Close: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13729
(Fix firefox misrendering when gfx.wayland.hdr option is true)
Backport-to: 25.2
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37098>
If no external/llvm-project directory is present, build with SwiftShader’s
static LLVM library if available. This can simplify Mesa builds inside
AOSP.
Signed-off-by: Deborah Brouwer <deborah.brouwer@collabora.com>
Reviewed-by: Antonio Ospite <antonio.ospite@collabora.com>
Reviewed-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37607>
If the (NIR) destination is a register (i.e., not an SSA value), the
destination of the BRW instruction will not be is_scalar. This occurs in
some shaders in Final Fantasy XVI (and
finalfantasytype0_1.rdc.2826e29da3722a83.1.foz).
If the destination is not is_scalar, revert most of this code to the
state previous to f3593df877. This means
- Allocate a SIMD1 register and UNDEF it.
- Emit a SIMD1 MOV_RELOC_IMM to that register.
- Emit an additional MOV to expand the SIMD1 result.
Closes: #12520
Fixes: f3593df877 ("brw/nir: Treat load_reloc_const_intel as convergent")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37384>
