mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-02-03 13:00:37 +01:00
pvr, pco: add remaining support for eds2 & 3
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com> Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37512>
This commit is contained in:
parent
17468aee4b
commit
63c4ecfae0
7 changed files with 56 additions and 31 deletions
|
|
@ -499,7 +499,7 @@ Vulkan 1.3 -- all DONE: anv, hk, lvp, nvk, panvk/v10+, radv, tu, vn, v3dv
|
|||
VK_KHR_zero_initialize_workgroup_memory DONE (anv, hasvk, lvp, nvk, panvk, radv, tu, v3dv, vn)
|
||||
VK_EXT_4444_formats DONE (anv, hasvk, lvp, nvk, panvk, radv, tu, v3dv, vn)
|
||||
VK_EXT_extended_dynamic_state DONE (anv, hasvk, lvp, nvk, panvk, pvr, radv, tu, v3dv, vn)
|
||||
VK_EXT_extended_dynamic_state2 DONE (anv, hasvk, lvp, nvk, panvk, radv, tu, v3dv, vn)
|
||||
VK_EXT_extended_dynamic_state2 DONE (anv, hasvk, lvp, nvk, panvk, pvr, radv, tu, v3dv, vn)
|
||||
VK_EXT_inline_uniform_block DONE (anv, hasvk, lvp, nvk, panvk, radv, tu, v3dv, vn)
|
||||
VK_EXT_pipeline_creation_cache_control DONE (anv, hasvk, lvp, nvk, panvk, radv, tu, v3dv, vn)
|
||||
VK_EXT_pipeline_creation_feedback DONE (anv, hasvk, lvp, nvk, panvk, radv, tu, v3dv, vn)
|
||||
|
|
@ -616,7 +616,7 @@ Khronos extensions that are not part of any Vulkan version:
|
|||
VK_EXT_display_control DONE (anv, hasvk, nvk, panvk, radv, tu)
|
||||
VK_EXT_display_surface_counter DONE (anv, lvp, nvk, panvk, radv, tu, vn)
|
||||
VK_EXT_dynamic_rendering_unused_attachments DONE (anv, hk, lvp, nvk, radv, tu, vn)
|
||||
VK_EXT_extended_dynamic_state3 DONE (anv, hk, lvp, nvk, radv, tu, vn)
|
||||
VK_EXT_extended_dynamic_state3 DONE (anv, hk, lvp, nvk, pvr, radv, tu, vn)
|
||||
VK_EXT_external_memory_acquire_unmodified DONE (anv, radv, vn)
|
||||
VK_EXT_external_memory_dma_buf DONE (anv, hasvk, hk, lvp, nvk, panvk, pvr, radv, tu, v3dv, vn)
|
||||
VK_EXT_external_memory_host DONE (anv, dzn, hasvk, lvp, radv)
|
||||
|
|
|
|||
|
|
@ -124,8 +124,6 @@ typedef struct _pco_fs_data {
|
|||
} uses;
|
||||
|
||||
struct {
|
||||
bool alpha_to_one;
|
||||
bool sample_mask;
|
||||
bool color_write_enable;
|
||||
} meta_present;
|
||||
} pco_fs_data;
|
||||
|
|
|
|||
|
|
@ -754,15 +754,10 @@ static bool is_load_sample_mask(const nir_instr *instr,
|
|||
}
|
||||
|
||||
static nir_def *
|
||||
lower_load_sample_mask(nir_builder *b, nir_instr *instr, void *cb_data)
|
||||
lower_load_sample_mask(nir_builder *b, nir_instr *instr, UNUSED void *cb_data)
|
||||
{
|
||||
struct pfo_state *state = cb_data;
|
||||
|
||||
b->cursor = nir_before_instr(instr);
|
||||
|
||||
if (!state->fs->meta_present.sample_mask)
|
||||
return nir_imm_int(b, 0xffff);
|
||||
|
||||
nir_def *smp_msk =
|
||||
nir_ubitfield_extract_imm(b, nir_load_fs_meta_pco(b), 9, 16);
|
||||
|
||||
|
|
@ -843,11 +838,12 @@ bool pco_nir_pfo(nir_shader *shader, pco_fs_data *fs)
|
|||
/* TODO: instead of doing multiple passes, probably better to just cache all
|
||||
* the stores
|
||||
*/
|
||||
if (fs->meta_present.alpha_to_one)
|
||||
if (!shader->info.internal) {
|
||||
progress |= nir_shader_lower_instructions(shader,
|
||||
is_frag_color_out,
|
||||
lower_alpha_to_one,
|
||||
&state);
|
||||
}
|
||||
|
||||
if (fs->meta_present.color_write_enable)
|
||||
progress |= nir_shader_lower_instructions(shader,
|
||||
|
|
@ -864,7 +860,7 @@ bool pco_nir_pfo(nir_shader *shader, pco_fs_data *fs)
|
|||
progress |= nir_shader_lower_instructions(shader,
|
||||
is_load_sample_mask,
|
||||
lower_load_sample_mask,
|
||||
&state);
|
||||
NULL);
|
||||
|
||||
util_dynarray_fini(&state.stores);
|
||||
util_dynarray_fini(&state.loads);
|
||||
|
|
|
|||
|
|
@ -2126,6 +2126,9 @@ static pco_instr *trans_intr(trans_ctx *tctx, nir_intrinsic_instr *intr)
|
|||
break;
|
||||
|
||||
case nir_intrinsic_load_fs_meta_pco:
|
||||
assert(tctx->stage == MESA_SHADER_FRAGMENT);
|
||||
assert(tctx->shader->data.fs.meta.count > 0);
|
||||
|
||||
return pco_mov(&tctx->b,
|
||||
dest,
|
||||
pco_ref_hwreg(tctx->shader->data.fs.meta.start,
|
||||
|
|
|
|||
|
|
@ -6248,7 +6248,9 @@ static inline bool pvr_ppp_dynamic_state_isp_faces_and_control_dirty(
|
|||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_RS_LINE_WIDTH) ||
|
||||
BITSET_TEST(dynamic_dirty,
|
||||
MESA_VK_DYNAMIC_RS_RASTERIZER_DISCARD_ENABLE) ||
|
||||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES);
|
||||
BITSET_TEST(dynamic_dirty,
|
||||
MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES) ||
|
||||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_MS_SAMPLE_MASK);
|
||||
}
|
||||
|
||||
static inline bool
|
||||
|
|
@ -6278,6 +6280,7 @@ pvr_ppp_state_update_required(const struct pvr_cmd_buffer *cmd_buffer)
|
|||
state->push_consts[PVR_STAGE_ALLOCATION_FRAGMENT].dirty ||
|
||||
pvr_ppp_dynamic_state_isp_faces_and_control_dirty(dynamic_dirty) ||
|
||||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_RS_DEPTH_BIAS_FACTORS) ||
|
||||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_RS_DEPTH_CLAMP_ENABLE) ||
|
||||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_VP_SCISSORS) ||
|
||||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_VP_SCISSOR_COUNT) ||
|
||||
BITSET_TEST(dynamic_dirty, MESA_VK_DYNAMIC_VP_VIEWPORTS) ||
|
||||
|
|
|
|||
|
|
@ -213,6 +213,8 @@ static void pvr_physical_device_get_supported_extensions(
|
|||
.EXT_depth_clamp_zero_one = true,
|
||||
.EXT_depth_clip_enable = true,
|
||||
.EXT_extended_dynamic_state = true,
|
||||
.EXT_extended_dynamic_state2 = true,
|
||||
.EXT_extended_dynamic_state3 = true,
|
||||
.EXT_external_memory_dma_buf = true,
|
||||
.EXT_host_query_reset = true,
|
||||
.EXT_image_2d_view_of_3d = true,
|
||||
|
|
@ -378,6 +380,44 @@ static void pvr_physical_device_get_supported_features(
|
|||
/* Vulkan 1.3 / VK_EXT_extended_dynamic_state */
|
||||
.extendedDynamicState = true,
|
||||
|
||||
/* Vulkan 1.3 / VK_EXT_extended_dynamic_state2 */
|
||||
.extendedDynamicState2 = true,
|
||||
.extendedDynamicState2LogicOp = false,
|
||||
.extendedDynamicState2PatchControlPoints = false,
|
||||
|
||||
/* VK_EXT_extended_dynamic_state3 */
|
||||
.extendedDynamicState3TessellationDomainOrigin = false,
|
||||
.extendedDynamicState3DepthClampEnable = false,
|
||||
.extendedDynamicState3PolygonMode = false,
|
||||
.extendedDynamicState3RasterizationSamples = true,
|
||||
.extendedDynamicState3SampleMask = true,
|
||||
.extendedDynamicState3AlphaToCoverageEnable = false,
|
||||
.extendedDynamicState3AlphaToOneEnable = true,
|
||||
.extendedDynamicState3LogicOpEnable = false,
|
||||
.extendedDynamicState3ColorBlendEnable = false,
|
||||
.extendedDynamicState3ColorBlendEquation = false,
|
||||
.extendedDynamicState3ColorWriteMask = false,
|
||||
.extendedDynamicState3RasterizationStream = false,
|
||||
.extendedDynamicState3ConservativeRasterizationMode = false,
|
||||
.extendedDynamicState3ExtraPrimitiveOverestimationSize = false,
|
||||
.extendedDynamicState3DepthClipEnable = false,
|
||||
.extendedDynamicState3SampleLocationsEnable = false,
|
||||
.extendedDynamicState3ColorBlendAdvanced = false,
|
||||
.extendedDynamicState3ProvokingVertexMode = false,
|
||||
.extendedDynamicState3LineRasterizationMode = false,
|
||||
.extendedDynamicState3LineStippleEnable = false,
|
||||
.extendedDynamicState3DepthClipNegativeOneToOne = false,
|
||||
.extendedDynamicState3ViewportWScalingEnable = false,
|
||||
.extendedDynamicState3ViewportSwizzle = false,
|
||||
.extendedDynamicState3CoverageToColorEnable = false,
|
||||
.extendedDynamicState3CoverageToColorLocation = false,
|
||||
.extendedDynamicState3CoverageModulationMode = false,
|
||||
.extendedDynamicState3CoverageModulationTableEnable = false,
|
||||
.extendedDynamicState3CoverageModulationTable = false,
|
||||
.extendedDynamicState3CoverageReductionMode = false,
|
||||
.extendedDynamicState3RepresentativeFragmentTestEnable = false,
|
||||
.extendedDynamicState3ShadingRateImageEnable = false,
|
||||
|
||||
/* Vulkan 1.2 / VK_EXT_host_query_reset */
|
||||
.hostQueryReset = true,
|
||||
|
||||
|
|
@ -712,6 +752,9 @@ static bool pvr_physical_device_get_properties(
|
|||
.patch = 4,
|
||||
},
|
||||
|
||||
/* VK_EXT_extended_dynamic_state3 */
|
||||
.dynamicPrimitiveTopologyUnrestricted = false,
|
||||
|
||||
/* VK_EXT_provoking_vertex */
|
||||
.provokingVertexModePerPipeline = true,
|
||||
.transformFeedbackPreservesTriangleFanProvokingVertex = false,
|
||||
|
|
|
|||
|
|
@ -1804,8 +1804,6 @@ static void pvr_alloc_vs_varyings(pco_data *data, nir_shader *nir)
|
|||
static void pvr_alloc_fs_sysvals(pco_data *data, nir_shader *nir)
|
||||
{
|
||||
BITSET_DECLARE(system_values_read, SYSTEM_VALUE_MAX);
|
||||
bool has_meta = false;
|
||||
|
||||
BITSET_COPY(system_values_read, nir->info.system_values_read);
|
||||
|
||||
gl_system_value sys_vals[] = {
|
||||
|
|
@ -1849,12 +1847,6 @@ static void pvr_alloc_fs_sysvals(pco_data *data, nir_shader *nir)
|
|||
check_unused_sysvals(system_values_read);
|
||||
assert(BITSET_IS_EMPTY(system_values_read));
|
||||
|
||||
has_meta |= data->fs.meta_present.alpha_to_one;
|
||||
has_meta |= data->fs.meta_present.sample_mask;
|
||||
has_meta |= data->fs.meta_present.color_write_enable;
|
||||
if (!has_meta)
|
||||
return;
|
||||
|
||||
data->fs.meta = (pco_range){
|
||||
.start = data->common.shareds,
|
||||
.count = 1,
|
||||
|
|
@ -2495,16 +2487,6 @@ pvr_preprocess_shader_data(pco_data *data,
|
|||
|
||||
data->fs.uses.alpha_to_coverage = state->ms->alpha_to_coverage_enable;
|
||||
|
||||
if (BITSET_TEST(state->dynamic, MESA_VK_DYNAMIC_MS_ALPHA_TO_ONE_ENABLE) ||
|
||||
(state->ms && state->ms->alpha_to_one_enable)) {
|
||||
data->fs.meta_present.alpha_to_one = true;
|
||||
}
|
||||
|
||||
if (BITSET_TEST(state->dynamic, MESA_VK_DYNAMIC_MS_SAMPLE_MASK) ||
|
||||
(state->ms && state->ms->sample_mask != 0xffff)) {
|
||||
data->fs.meta_present.sample_mask = true;
|
||||
}
|
||||
|
||||
if (BITSET_TEST(state->dynamic, MESA_VK_DYNAMIC_CB_COLOR_WRITE_ENABLES) ||
|
||||
(state->cb && state->cb->color_write_enables !=
|
||||
BITFIELD_MASK(MESA_VK_MAX_COLOR_ATTACHMENTS))) {
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue