214263 commits

This branch

This branch

All branches

Author	SHA1	Message	Date
Qiang Yu	11f2babddc	mesa,gallium: not touch TS when internal draws ... TS does not affect vertex pipeline draws. We keep mesh shader before radeonsi is ready. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:19 +00:00
Qiang Yu	4711fb711c	gallium/blitter: no need to save TS state ... TS does not affect blitter currently. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:19 +00:00
Qiang Yu	71e0895715	mesa,radeonsi: add comments about vertex and mesh pipeline shader states ... They are exclusive in mesa state tracker currently, so add some comments and assertions for developers. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:19 +00:00
Qiang Yu	dcf2399e6f	radeonsi: save mesh shader when blit ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:19 +00:00
Qiang Yu	ffc3d430db	radeonsi: simplify si_update_rasterized_prim while handle mesh shader ... Otherwise mesh shader ends in the "else" section. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:19 +00:00
Qiang Yu	56a437183a	radeonsi: si_get_vs support mesh shader ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:19 +00:00
Qiang Yu	7e83962e85	radeonsi: update scratch va for mesh shader ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:19 +00:00
Qiang Yu	de4fb088d3	radeonsi: share some vertex pipe function with mesh pipe ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:18 +00:00
Qiang Yu	e6e21dfbf2	radeonsi: kill outputs for mesh shader ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:18 +00:00
Qiang Yu	4c315bdbfa	radeonsi: lower task/mesh shader io to mem ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:18 +00:00
Qiang Yu	5931dbf7ac	radeonsi: add task info to screen ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:18 +00:00
Qiang Yu	73aebeec42	radeonsi: no ngg culling for mesh shader ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:17 +00:00
Qiang Yu	74894150f1	radeonsi: init pm4 state for mesh shader ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:17 +00:00
Qiang Yu	ce6a1e7563	radeonsi: init mesh shader args ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:16 +00:00
Qiang Yu	2038134efc	radeonsi: calc workgroup size for mesh shader ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:15 +00:00
Qiang Yu	977a3f45bf	radeonsi: add task/mesh shader info to si_shader_info ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:15 +00:00
Qiang Yu	8659666089	radeonsi: add si_mesh_resources_add_all_to_bo_list ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:14 +00:00
Qiang Yu	b533d39b95	radeonsi: inline uniform support mesh shader ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:14 +00:00
Qiang Yu	8a3ef188c2	radeonsi: add context shader state for mesh shader ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:13 +00:00
Qiang Yu	24d7c9a2a8	radeonsi: handle mesh shader when si_create_shader ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:12 +00:00
Qiang Yu	f06a1b0d07	radeonsi: enlarge SI_NUM_SHADERS for mesh shader ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37505>	2025-10-17 03:52:12 +00:00
Mike Blumenkrantz	f74cf45078	zink: consistently set/unset msrtss in begin_rendering ... this has to always be set or unset, never persistent from previous renderpass Fixes: 5080f2b6f5 ("zink: disable msrtss handling when blitting") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37923>	2025-10-16 22:22:34 -04:00
Marek Olšák	733ba77bfe	r300: fix DXTC blits ... Fixes: 9d359c6d10 - gallium: delete pipe_surface::width and pipe_surface::height Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37912>	2025-10-16 22:33:50 +00:00
Gert Wollny	ba35ac29b6	r600/sfn: drop range pinning for registers after RA ... Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37847>	2025-10-16 20:57:18 +00:00
Gert Wollny	5962add398	r600/sfn: correct register interference range ... If a life range of one register starts in the same instruction where the life range of another register ends, then the two ranges don't overlap. v2: Fix test Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37847>	2025-10-16 20:57:18 +00:00
Dylan Baker	a1b6dbcd67	docs: update calendar for 25.3.0-rc1 ... Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37921>	2025-10-16 20:52:31 +00:00
José Roberto de Souza	ad86a666ae	anv: Add support for low latency hint on Xe KMD ... This hint tells KMD and firmware to turn into low latency but high power usage mode. i915 already had it now it was implemented in Xe KMD. Reviewed-by: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33214>	2025-10-16 20:23:21 +00:00
José Roberto de Souza	0ba6a0a23b	intel/dev: Add supports_low_latency_hint to intel_device_info ... Lets query if this feature is supported only once, also in the next patches support for this feature will be added to Xe KMD. Reviewed-by: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33214>	2025-10-16 20:23:21 +00:00
Xaver Hugl	892cf427a0	vulkan/wsi: require extended target volume support for scRGB ... It's hardly going to be useful without that Signed-off-by: Xaver Hugl <xaver.hugl@kde.org> Fixes: 4b663d56 ("vulkan/wsi: implement support for VK_EXT_hdr_metadata on Wayland") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37920>	2025-10-16 19:58:02 +00:00
Mary Guillemard	e3d9c5da2a	mr-label-maker: Remove mapi label ... It doesn't exist anymore. Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>	2025-10-16 19:25:35 +00:00
Mary Guillemard	f65756a31b	mr-label-maker: Add poly ... Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>	2025-10-16 19:25:35 +00:00
Mary Guillemard	b2accf86d1	poly: Migrate AGX's GS/TESS emulation to common code ... This moves most of the code to a new home: src/poly. Most precomp kernels logic that could be moved are provided by poly now. Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com> Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>	2025-10-16 19:25:35 +00:00
Mary Guillemard	8048004238	asahi/gs: Reuse GS shader compiler options ... Avoid importing internal bits Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>	2025-10-16 19:25:35 +00:00
Mary Guillemard	6f73533094	asahi,nir: Stop relying on zero and scratch page in GS/TESS code ... Introduce new NIR intrinsics to handle getting a "sink" read-only address and another intrinsic to handle conversion of address to read-write (allowing implementation to replace the "sink" read-only with another address like required for Asahi) Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>	2025-10-16 19:25:35 +00:00
Mary Guillemard	60e5abdbaa	asahi: Move compiler preprocess out of agx_nir_lower_gs ... We run agx_preprocess_nir as the last step of each new compute shaders in agx_nir_lower_gs but we could move this out of the pass and makes it the driver responsability to call it. Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>	2025-10-16 19:25:35 +00:00
Mary Guillemard	a427581c4d	asahi/gs: Remove agx_nir_* prefix around static functions ... Only a small detail but git will not go too crazy when I move everything around at least. Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>	2025-10-16 19:25:35 +00:00
Mary Guillemard	71c4943c37	compiler: rename vs.tes_agx bit to vs.tes_poly ... Preparing to move AGX's GS/TESS lowering code. Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>	2025-10-16 19:25:35 +00:00
Mary Guillemard	1e0c18d6cf	nir: Rename stat_query_address_agx to stat_query_address_poly ... This is used by the geometry lowering that we are going to move to common code. Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>	2025-10-16 19:25:35 +00:00
Mary Guillemard	8a25b88d69	asahi/libagx: Do not expose anything not use externaly ... No need to actually generate NIR bindings for anything we don't need to. We are going to copy most of this in Panfrost and that will be required there... Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>	2025-10-16 19:25:35 +00:00
Mary Guillemard	29f348941d	asahi/libagx: Stop exposing fake entrypoint _libagx_prefix_sum ... This was a hack to allow things to build but still could break in the future, let comply by passing scratch as an argument instead. Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37914>	2025-10-16 19:25:35 +00:00
Lionel Landwerlin	c20e2733bf	Revert "brw: add serialize send stats" ... This reverts commit b8ae4ede60 now that we have a cycle estimation accounting. Reviewed-by: Alyssa Anne Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37816>	2025-10-16 18:55:06 +00:00
Lionel Landwerlin	14683a045b	brw: account for disabled SEND fused message in cycle computation ... This is an alternative Curro proposed to counting the number of serialized messages. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Alyssa Anne Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37816>	2025-10-16 18:55:06 +00:00
Job Noorman	3b2f7ed918	ci,marge_queue: read token from file by default ... This allows token to be stored in ~/.config/gitlab-token instead of passing them as an argument. Signed-off-by: Job Noorman <jnoorman@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37916>	2025-10-16 17:40:51 +00:00
Lionel Landwerlin	77fb8fb062	anv: fix image-to-image copies of TileW images ... The intermediate buffer between the 2 images is linear, its stride should be a function of the tile's logical width. Normally this should map to the values reported by ISL except for TileW where for some reason it was decided to report 128 for TileW instead of the actual 64 size (see isl_tiling_get_info() ISL_TILING_W case) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37902>	2025-10-16 17:07:32 +00:00
Job Noorman	75604ff945	ir3: allow (neg) on sel.b on a6xx gen4+ ... Setting the (neg) flag on a sel.b source behaves as fneg on a6xx gen4+. Totals from 22733 (13.80% of 164705) affected shaders: MaxWaves: 277060 -> 277292 (+0.08%); split: +0.11%, -0.03% Instrs: 17676148 -> 17634471 (-0.24%); split: -0.47%, +0.24% CodeSize: 34824114 -> 34693740 (-0.37%); split: -0.44%, +0.06% NOPs: 3466984 -> 3487984 (+0.61%); split: -1.17%, +1.78% MOVs: 521091 -> 522791 (+0.33%); split: -1.87%, +2.20% Full: 315929 -> 315699 (-0.07%); split: -0.09%, +0.02% (ss): 473545 -> 472947 (-0.13%); split: -1.36%, +1.23% (sy): 195612 -> 195743 (+0.07%); split: -1.00%, +1.07% (ss)-stall: 1928887 -> 1922757 (-0.32%); split: -1.96%, +1.64% (sy)-stall: 4965071 -> 4972119 (+0.14%); split: -1.43%, +1.57% STPs: 777 -> 762 (-1.93%) LDPs: 2168 -> 2117 (-2.35%) Preamble Instrs: 3465691 -> 3462635 (-0.09%); split: -0.09%, +0.00% Last helper: 4666320 -> 4593331 (-1.56%); split: -2.81%, +1.24% Last baryf: 235724 -> 230049 (-2.41%); split: -4.56%, +2.15% Subgroup size: 2021248 -> 2021952 (+0.03%); split: +0.07%, -0.03% Cat0: 3792738 -> 3814197 (+0.57%); split: -1.08%, +1.64% Cat1: 757480 -> 759260 (+0.23%); split: -1.28%, +1.52% Cat2: 6960677 -> 6897218 (-0.91%) Cat6: 78290 -> 78224 (-0.08%) Cat7: 422101 -> 420710 (-0.33%); split: -1.41%, +1.09% Signed-off-by: Job Noorman <jnoorman@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37906>	2025-10-16 16:46:18 +00:00
Job Noorman	eaef6d048b	ir3: add has_sel_b_fneg compiler flag ... a6xx+ support (neg) on sel.b which behaves as fneg. Add a compiler flag for this. Signed-off-by: Job Noorman <jnoorman@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37906>	2025-10-16 16:46:18 +00:00
Job Noorman	c44f8fe7f7	ir3: move ir3_catN_absneg to ir3.c ... The following commit needs to use ir3_compiler whose definition isn't available in ir3.h. Signed-off-by: Job Noorman <jnoorman@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37906>	2025-10-16 16:46:18 +00:00
David Rosca	09ff0fa005	frontends/va: Move remainig processing functions to postproc.c ... Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37545>	2025-10-16 16:33:15 +00:00
David Rosca	7a5270d4df	frontends/va: Move decode functions to separate file ... Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37545>	2025-10-16 16:33:15 +00:00
David Rosca	ba0a059129	frontends/va: Move encode functions to separate file ... Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37545>	2025-10-16 16:33:15 +00:00