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Author SHA1 Message Date
Faith Ekstrand
2febabbd3c kraid: Handle nir_op_mov/vec/[un]pack 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
 2026-06-02 21:19:26 +00:00
Faith Ekstrand
765b89ed2e kraid: Handle load_const instructions 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
 2026-06-02 21:19:26 +00:00
Faith Ekstrand
6cbdc95f2a kraid: Parse the NIR CFG 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
 2026-06-02 21:19:26 +00:00
Faith Ekstrand
102795ce74 kraid: Start parsing NIR shaders 
The parser doesn't actually do anything yet but now we have a framework
we can add stuff to.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
 2026-06-02 21:19:26 +00:00
Faith Ekstrand
f8a4b912d0 kraid: Add a builder 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
 2026-06-02 21:19:26 +00:00
Faith Ekstrand
45c7868e39 kraid: Add Instr, BasicBlock, and Shader structs 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
 2026-06-02 21:19:26 +00:00
Faith Ekstrand
e07f0b567c kraid: Add an Opcode trait and Op enum 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
 2026-06-02 21:19:26 +00:00
Faith Ekstrand
3de388f652 kraid: Add Src/Dst data types 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
 2026-06-02 21:19:26 +00:00
Faith Ekstrand
eaead919d5 kraid: Add SSAValue and SSARef structs 
These is based on NAK but modified for what we need on Mali.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
 2026-06-02 21:19:26 +00:00
Faith Ekstrand
292ec991a0 kraid: Add a swizzle struct 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
 2026-06-02 21:19:26 +00:00
Faith Ekstrand
326c7b4382 kraid: Add DataType and NumericType enums 
Most of the implementation of DataType is in a proc macro so we can walk
over all the variants programatically instead of having to hand-type a
bunch of potentially error-prone code.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
 2026-06-02 21:19:26 +00:00
Faith Ekstrand
9b33ba5a73 kraid: Add a GPU model abstraction 
This is sort of our version of pan_model.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
 2026-06-02 21:19:26 +00:00
Faith Ekstrand
d88b53075a panfrost: Add the basis for the new Kraid compiler 
This adds some mostly empty rust files, bindings, meson bits, and a call
into kraid from the bifrost compiler, guarded by PAN_USE_KRAID=1.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
 2026-06-02 21:19:25 +00:00
Daniel Stone
abdd97e540 symbols-check: Ignore more pthread symbols 
We have yet more pthread-related symbols to be marked as weak, as well
as statx as a fallback for older systems. Add these to the list along
with the rest of the related symbols, since we can't stop glibc from
exporting them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
 2026-06-02 21:19:25 +00:00
Faith Ekstrand
2a416638a8 panfrost: Initial rust build system support 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
 2026-06-02 21:19:25 +00:00
Marek Olšák
a56079b302 radv: emit_rast_samples_state uses uses_vrs_attachment only on gfx11+ 
it's not used by previous gens

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41768>
 2026-06-02 20:38:06 +00:00
Marek Olšák
dd8ca1d94d radv: make RAST_SAMPLES_STATE dirty in CmdBeginRendering only on gfx12+ 
older gens don't use the render state in radv_emit_rast_samples_state

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41768>
 2026-06-02 20:38:06 +00:00
Marek Olšák
47398b57de ac/nir/lower_ps_early: remove now-unused lowering of sample_mask_in 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41768>
 2026-06-02 20:38:06 +00:00
Marek Olšák
4b5852ad3f radeonsi: use ac_nir_lower_sample_mask_in 
to use the same code as RADV

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41768>
 2026-06-02 20:38:06 +00:00
Marek Olšák
d5c4fb763a radv: fix an inefficiency where the ANCILLARY PS VGPR was enabled but unused 
This was probably enabled because sample_mask_in lowering used sample_id.
Now that the lowering is done before shader info gathering, this
inefficiency can be removed.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41768>
 2026-06-02 20:38:06 +00:00
Marek Olšák
7ee7f889b4 radv: enable SAMPLE_COVERAGE PS VGPR dynamically 
This increases the PS wave launch rate if it decreases the number of
initialized VGPRs to an even number depending on other states.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41768>
 2026-06-02 20:38:06 +00:00
Marek Olšák
13547b1f87 radv: switch to ac_nir_lower_sample_mask_in 
load_use_sample_mask_in_amd will be fully implemented in a later commit.

This is already more efficient because of using helper_invocation
in the pass.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41768>
 2026-06-02 20:38:05 +00:00
Marek Olšák
e5723a61f2 ac/nir: add a new pass ac_nir_lower_sample_mask_in 
This covers all the optimal lowering cases of sample_mask_in.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41768>
 2026-06-02 20:38:05 +00:00
Marek Olšák
146d3d7e1f ac/nir/lower_ps_early: assume frag_coord_is_center is always true 
RADV will never use this option because it lowers sample_pos in its own
pass.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41768>
 2026-06-02 20:38:05 +00:00
Marek Olšák
c42e4a2fba ac/nir/lower_ps_early: remove obsolete comment 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41768>
 2026-06-02 20:38:04 +00:00
Marek Olšák
ea5352b7d7 radv: ignore color attachment samples for ps_iter_samples 
Sample shading is only affected by the number of rasterization samples.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41768>
 2026-06-02 20:38:04 +00:00
Gleb Popov
6ae0114b05 Rename the CACHE_LINE_SIZE define to MESA_CACHE_LINE_SIZE 
The former clashes with a define with the same name that comes from FreeBSD
base headers.

Closes #5737

Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41906>
 2026-06-02 20:04:20 +00:00
Karol Herbst
2ea31794f0 rusticl/program: wrap compiler option parsing
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
Details
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details 
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41905>
 2026-06-02 19:30:23 +00:00
Karol Herbst
01de0ff26f rusticl/program: store log as a CString 
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41905>
 2026-06-02 19:30:23 +00:00
Karol Herbst
d7674245e2 rusticl/kernel: store kernel names as CString 
There is no reasons to have this as a rust string.

Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41905>
 2026-06-02 19:30:23 +00:00
Karol Herbst
8711a88d96 rusticl/util: add Traits to help with usage of CString 
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41905>
 2026-06-02 19:30:22 +00:00
Karol Herbst
4fa798516e meson: enable more rust 2024 lints 
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41905>
 2026-06-02 19:30:22 +00:00
Emma Anholt
aa26be6ea9 tu: Move to using drirc_gen. 
Slight reduction in boilerplate (driconf.h definition, tu_device.cc
parsing, tu_device.h instance definitions), plus validation that you don't
typo between 00-turnip-defaults.conf and tu_device.cc parsing.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41877>
 2026-06-02 18:49:48 +00:00
Emma Anholt
ae2cc693f8 util/drirc_gen: Make the header usable from C++. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41877>
 2026-06-02 18:49:48 +00:00
Emma Anholt
2595e4a972 util/drirc_gen: Move the common VK WSI options to a core helper function. 
I didn't want to copy and paste this again for tu.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41877>
 2026-06-02 18:49:48 +00:00
Emma Anholt
3ad3bb33d1 util/drirc_gen: Reduce manual importing of functions. 
I wanted to use another common function, and having to manual import it
felt silly given that we're a drirc_gen user.  But we are limited because
we don't have the common code in the system path at startup, so we can't
just import it at module level.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41877>
 2026-06-02 18:49:48 +00:00
Emma Anholt
a514d1e7ec radv/drirc_gen: Clean up the dependency handling. 
This matches Intel -- we get a dependency on the conf file from it
appearing as a command arg, and drirc_gen.py from it being in the inputs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41877>
 2026-06-02 18:49:48 +00:00
Emma Anholt
2ac718c1b8 util/drirc_gen: Add a little documentation of what this does. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41877>
 2026-06-02 18:49:48 +00:00
Ian Romanick
dcfc90a8fc nir/algebraic: Convert bcsel of addition to addition of b2i or b2f 
Recent changes to continue handling in loops results in many cases of

    loop {
        ...
	if (...) {
	    do_continue = true; // was continue;
	}

	i = do_continue ? i : i + 1;
    }

I noticed this while investigating mesa#15154. Unfortunately, this
doesn't fix the performance regressions noted in that issue.

One fragment shader in XCOM: Enemy Unknown doesn't like this change. :(

v2: Drop _nsz from a couple bcsel patterns where it is not needed.
Suggested by Georg.

v3: Drop ~ from the last two fadd patterns. Suggested by Georg. Update
expected checksum for plot3d-v2.trace on many platforms.

shader-db:

All Iris platforms had similar results. (Lunar Lake shown)
total instructions in shared programs: 17089936 -> 17086837 (-0.02%)
instructions in affected programs: 864928 -> 861829 (-0.36%)
helped: 696 / HURT: 110

total cycles in shared programs: 864096306 -> 863913752 (-0.02%)
cycles in affected programs: 345726340 -> 345543786 (-0.05%)
helped: 620 / HURT: 196

total spills in shared programs: 3318 -> 3319 (0.03%)
spills in affected programs: 14 -> 15 (7.14%)
helped: 0 / HURT: 1

total fills in shared programs: 1604 -> 1606 (0.12%)
fills in affected programs: 28 -> 30 (7.14%)
helped: 0 / HURT: 1

total sends in shared programs: 876852 -> 876850 (<.01%)
sends in affected programs: 6 -> 4 (-33.33%)
helped: 2 / HURT: 0

fossil-db:

Lunar Lake
Totals:
Instrs: 914468779 -> 914215874 (-0.03%); split: -0.03%, +0.00%
CodeSize: 12885732160 -> 12881939568 (-0.03%); split: -0.04%, +0.01%
Cycle count: 100100279922 -> 100096866800 (-0.00%); split: -0.05%, +0.04%
Spill count: 3459786 -> 3459693 (-0.00%); split: -0.01%, +0.01%
Fill count: 4909835 -> 4909177 (-0.01%); split: -0.04%, +0.03%
Max live registers: 191819298 -> 191822052 (+0.00%); split: -0.00%, +0.00%
Max dispatch width: 48511264 -> 48510608 (-0.00%); split: +0.00%, -0.00%
Non SSA regs after NIR: 136334891 -> 136301926 (-0.02%); split: -0.03%, +0.00%

Totals from 37416 (1.87% of 2003390) affected shaders:
Instrs: 53346249 -> 53093344 (-0.47%); split: -0.48%, +0.01%
CodeSize: 775396384 -> 771603792 (-0.49%); split: -0.60%, +0.11%
Cycle count: 32275003526 -> 32271590404 (-0.01%); split: -0.14%, +0.13%
Spill count: 569304 -> 569211 (-0.02%); split: -0.05%, +0.03%
Fill count: 620240 -> 619582 (-0.11%); split: -0.31%, +0.21%
Max live registers: 6712048 -> 6714802 (+0.04%); split: -0.01%, +0.05%
Max dispatch width: 893344 -> 892688 (-0.07%); split: +0.10%, -0.17%
Non SSA regs after NIR: 7191473 -> 7158508 (-0.46%); split: -0.49%, +0.03%

Meteor Lake and DG2 had similar results. (Meteor Lake shown)
Totals:
Instrs: 985625036 -> 985366432 (-0.03%); split: -0.03%, +0.00%
CodeSize: 16446268768 -> 16442606864 (-0.02%); split: -0.03%, +0.01%
Cycle count: 91278956920 -> 91272371300 (-0.01%); split: -0.07%, +0.06%
Spill count: 3713935 -> 3714003 (+0.00%); split: -0.00%, +0.00%
Fill count: 5001514 -> 5001259 (-0.01%); split: -0.03%, +0.02%
Max live registers: 120736970 -> 120738919 (+0.00%); split: -0.00%, +0.00%
Max dispatch width: 37827808 -> 37829472 (+0.00%); split: +0.01%, -0.00%
Non SSA regs after NIR: 160606595 -> 160573270 (-0.02%); split: -0.02%, +0.00%

Totals from 38664 (1.71% of 2265137) affected shaders:
Instrs: 53621392 -> 53362788 (-0.48%); split: -0.49%, +0.01%
CodeSize: 932994544 -> 929332640 (-0.39%); split: -0.52%, +0.13%
Cycle count: 24442489628 -> 24435904008 (-0.03%); split: -0.25%, +0.22%
Spill count: 550952 -> 551020 (+0.01%); split: -0.02%, +0.03%
Fill count: 525010 -> 524755 (-0.05%); split: -0.27%, +0.23%
Max live registers: 3594805 -> 3596754 (+0.05%); split: -0.01%, +0.07%
Max dispatch width: 510928 -> 512592 (+0.33%); split: +0.47%, -0.14%
Non SSA regs after NIR: 7652247 -> 7618922 (-0.44%); split: -0.46%, +0.03%

Tiger Lake, Ice Lake, and Skylake had similar results. (Tiger Lake shown)
Totals:
Instrs: 997905938 -> 997771670 (-0.01%); split: -0.01%, +0.00%
CodeSize: 13990460928 -> 13988346016 (-0.02%); split: -0.02%, +0.00%
Cycle count: 83465002175 -> 83456829524 (-0.01%); split: -0.02%, +0.01%
Spill count: 3815020 -> 3814879 (-0.00%); split: -0.01%, +0.00%
Fill count: 6561078 -> 6560768 (-0.00%); split: -0.01%, +0.00%
Max live registers: 121468149 -> 121468160 (+0.00%); split: -0.00%, +0.00%
Max dispatch width: 37914400 -> 37914624 (+0.00%); split: +0.00%, -0.00%
Non SSA regs after NIR: 155941530 -> 155944033 (+0.00%); split: -0.00%, +0.00%

Totals from 27771 (1.22% of 2273117) affected shaders:
Instrs: 31224666 -> 31090398 (-0.43%); split: -0.44%, +0.01%
CodeSize: 450250800 -> 448135888 (-0.47%); split: -0.57%, +0.10%
Cycle count: 15045135658 -> 15036963007 (-0.05%); split: -0.13%, +0.08%
Spill count: 406812 -> 406671 (-0.03%); split: -0.05%, +0.01%
Fill count: 391210 -> 390900 (-0.08%); split: -0.10%, +0.02%
Max live registers: 2592759 -> 2592770 (+0.00%); split: -0.02%, +0.02%
Max dispatch width: 383888 -> 384112 (+0.06%); split: +0.23%, -0.17%
Non SSA regs after NIR: 4221402 -> 4223905 (+0.06%); split: -0.01%, +0.07%

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41871>
 2026-06-02 17:44:14 +00:00
Ian Romanick
daa38c1972 nir/opt_if: Merge if-statements with inverted conditions 
Cases like

    if (x) {
        ...
    } else {
        ...
    }
    if (!x) {
        ...
    } else {
        ...
    }

should be merged.

I don't know why Ice Lake is affected differetly by this commit.

v2: Add implementation of srcs_equal_or_logical_inverse after bad
rebase. That's what I get for rushing out an MR right before lunch.
Noticed by Georg.

shader-db:

Lunar Lake
No changes.

All other Iris platforms had simlar results. (Meteor Lake shown)
total cycles in shared programs: 882310108 -> 882311504 (<.01%)
cycles in affected programs: 74306 -> 75702 (1.88%)
helped: 4
HURT: 2
helped stats (abs) min: 2.0 max: 38.0 x̄: 11.00 x̃: 2
helped stats (rel) min: 0.02% max: 0.29% x̄: 0.09% x̃: 0.02%
HURT stats (abs)   min: 720.0 max: 720.0 x̄: 720.00 x̃: 720
HURT stats (rel)   min: 5.27% max: 5.27% x̄: 5.27% x̃: 5.27%
95% mean confidence interval for cycles value: -163.75 629.08
95% mean confidence interval for cycles %-change: -1.21% 4.61%
Inconclusive result (value mean confidence interval includes 0).

fossil-db:

All Intel platforms except Ice Lake had similar results. (Lunar Lake shown)
Totals:
Instrs: 914554534 -> 914546744 (-0.00%); split: -0.00%, +0.00%
CodeSize: 12887129264 -> 12886823808 (-0.00%); split: -0.00%, +0.00%
Send messages: 40220826 -> 40219429 (-0.00%); split: -0.00%, +0.00%
Cycle count: 100101810976 -> 100101804762 (-0.00%); split: -0.00%, +0.00%
Spill count: 3459811 -> 3459786 (-0.00%); split: -0.00%, +0.00%
Fill count: 4909877 -> 4909835 (-0.00%); split: -0.00%, +0.00%
Max live registers: 191837229 -> 191838000 (+0.00%); split: -0.00%, +0.00%
Max dispatch width: 48514400 -> 48514336 (-0.00%)
Non SSA regs after NIR: 136346777 -> 136343948 (-0.00%); split: -0.00%, +0.00%

Totals from 1937 (0.10% of 2003486) affected shaders:
Instrs: 3013550 -> 3005760 (-0.26%); split: -0.39%, +0.13%
CodeSize: 43169072 -> 42863616 (-0.71%); split: -0.81%, +0.10%
Send messages: 183171 -> 181774 (-0.76%); split: -0.82%, +0.06%
Cycle count: 126864798 -> 126858584 (-0.00%); split: -0.67%, +0.67%
Spill count: 7354 -> 7329 (-0.34%); split: -0.45%, +0.11%
Fill count: 5547 -> 5505 (-0.76%); split: -0.88%, +0.13%
Max live registers: 296895 -> 297666 (+0.26%); split: -0.04%, +0.30%
Max dispatch width: 41856 -> 41792 (-0.15%)
Non SSA regs after NIR: 545672 -> 542843 (-0.52%); split: -1.15%, +0.63%

Ice Lake
Totals:
Instrs: 996341606 -> 996312120 (-0.00%); split: -0.00%, +0.00%
CodeSize: 12563695936 -> 12563195200 (-0.00%); split: -0.00%, +0.00%
Send messages: 45911343 -> 45909063 (-0.00%); split: -0.00%, +0.00%
Cycle count: 82819362995 -> 82818778468 (-0.00%); split: -0.00%, +0.00%
Spill count: 2935451 -> 2935452 (+0.00%); split: -0.00%, +0.00%
Fill count: 5034267 -> 5034281 (+0.00%); split: -0.00%, +0.00%
Max live registers: 124672355 -> 124672961 (+0.00%); split: -0.00%, +0.00%
Max dispatch width: 41330808 -> 41330672 (-0.00%)
Non SSA regs after NIR: 160790466 -> 160785863 (-0.00%); split: -0.01%, +0.00%

Totals from 2163 (0.09% of 2327905) affected shaders:
Instrs: 4164788 -> 4135302 (-0.71%); split: -0.80%, +0.09%
CodeSize: 53351344 -> 52850608 (-0.94%); split: -0.95%, +0.01%
Send messages: 271164 -> 268884 (-0.84%); split: -0.84%, +0.00%
Cycle count: 145818114 -> 145233587 (-0.40%); split: -0.66%, +0.26%
Spill count: 7819 -> 7820 (+0.01%); split: -0.32%, +0.33%
Fill count: 7191 -> 7205 (+0.19%); split: -0.57%, +0.76%
Max live registers: 192403 -> 193009 (+0.31%); split: -0.08%, +0.40%
Max dispatch width: 34728 -> 34592 (-0.39%)
Non SSA regs after NIR: 570874 -> 566271 (-0.81%); split: -1.49%, +0.68%

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41871>
 2026-06-02 17:44:14 +00:00
Ian Romanick
e8cef4725d nir/opt_if: use nir_def_replace() instead of nir_def_rewrite_uses() 
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41871>
 2026-06-02 17:44:13 +00:00
Ian Romanick
4a37fda884 nir: Use nir_instr_remove_v in nir_def_replace 
The non _v version sets up and returns a nir_cursor that isn't
used. Skip that work by calling nir_instr_remove_v directly.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41871>
 2026-06-02 17:44:13 +00:00
Job Noorman
56a8225742 ir3: use a1.x addressing for ldg.k with dst 256 
Its dst uses 8 bits so cannot encode 256.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: e6529b54c0 ("ir3: add support for the ldg.k a1.x addressing mode")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41871>
 2026-06-02 17:44:13 +00:00
Rob Herring (Arm)
0972ef7d33 ethosu: Add performance counter debug output
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Add simple performance counter support as debug output. This is enough
to measure NPU cycles for networks.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40269>
 2026-06-02 17:07:08 +00:00
Tomeu Vizoso
83d0646d79 teflon/tests: make tflite stubs fail loudly with diagnostics 
Be more explicit when the stubs are used, even if that shouldn't happen
any more.

Reviewed-by: Maíra Canal <mcanal@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40269>
 2026-06-02 17:07:08 +00:00
Tomeu Vizoso
b33f0cc7fc teflon/tests: avoid loading build-tree tensorflow-lite stub at runtime 
It can be quite confusing to see the tests failing to load models
without knowing why. To avoid making people waste time with strace, link
with the stubs at build time but look for the actual implementation at
run time.

Reviewed-by: Maíra Canal <mcanal@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40269>
 2026-06-02 17:07:08 +00:00
Silvio Vilerino
31fe3637a2 mediafoundation: check for AUTO slice/tile only capable hardware 
Reviewed-by: Pohsiang (John) Hsu <pohhsu@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41947>
 2026-06-02 16:50:00 +00:00
Silvio Vilerino
ce05976385 d3d12: Support video encode AUTO slice/tile only capable hardware 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41947>
 2026-06-02 16:50:00 +00:00
Samuel Pitoiset
2e55357b33 radv: fix DGC with conditional rendering and task+mesh shaders 
While I was investigating some task+mesh random GPU hangs in CI, I
finally found a sequence that caused a test failure:

dEQP-VK.dgc.ext.graphics.mesh.conditional_rendering.general.classic_bind_with_count_buffer_condition_false_with_task_shader
dEQP-VK.dgc.ext.graphics.mesh.token_draw_count.monolithic_with_task_shader

Executing these two tests in a row caused the second one to always fail
(tested on NAVI33).

After investigating I figured out that only the DGC GFX IB was
predicated (with IB2) and the DGC ACE IB was always running, although
without any mesh draws to consume the task output. It seems the
hardware is confused if another task+mesh draw is dispatched after that,
and this could cause failures or GPU hangs.

Fix this by resetting the number of DGC sequences to 0 when conditional
rendering is used. This is the only option to emulate conditional
rendering with DGC and ACE.

This also likely fixes DGC+RT on compute queue.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41939>
 2026-06-02 16:23:18 +00:00
Rhys Perry
1301eef21d radv: fix usage of radv_nir_cmat_length 
This should be after we finalize desc.use.

Fixes FSR4 on RDNA3.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: ca0496bc26 ("radv: use load_deref_transpose_amd for transposed cooperative matrix loads")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41922>
 2026-06-02 15:57:14 +00:00