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Author SHA1 Message Date
Marek Olšák
2b3f551ed8 ac/nir: don't use load_esgs_vertex_stride_amd on gfx6-8 
An improvement for 9f1e6d8f70.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21641>
 2023-03-03 00:41:48 +00:00
Marek Olšák
79732416fd amd: query cache sizes from the kernel 
Also rename l1_cache_size -> tcp_cache_size. L1 means shader array cache.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21641>
 2023-03-03 00:41:48 +00:00
Marek Olšák
6e2e89e6d8 amd,radeonsi: change enabled_rb_mask to 64 bits 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21641>
 2023-03-03 00:41:48 +00:00
Marek Olšák
03ffb8d77c amd: update amdgpu_drm.h 
From kernel commit 817714d9665e.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21641>
 2023-03-03 00:41:48 +00:00
Rhys Perry
dc01f03d1b radv: remove is_internal pipeline creation parameter 
Instead, check if the cache is the meta shader cache. This catches the
shaders created by radv_create_radix_sort_u64().

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21606>
 2023-03-02 16:48:09 +00:00
Samuel Pitoiset
4ec6850210 radv: fix DCC decompress on GFX11 
The hardware requires one color output to be set by CB registers,
otherwise the DCC decompression does nothing.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8127
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8175
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8370
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21629>
 2023-03-02 16:03:31 +00:00
Tatsuyuki Ishi
57ab623f0b radv: Use common helpers to translate format in SDMA copy. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21585>
 2023-03-02 15:29:47 +00:00
Tatsuyuki Ishi
4f681d5e2c radv: Remove SDMA padding from copy helpers. 
These are handled in winsys already; no need to duplicate and complicate
the code paths.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21585>
 2023-03-02 15:29:47 +00:00
Tatsuyuki Ishi
e9a55b332a radv: SDMA v4 size field is size - 1 
After cross-checking with kernel and the old buffer copy code, it seems
that the size field should be size - 1 instead.

Fixes: 7b5ab48c40 ("radv: partial sdma support")

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21585>
 2023-03-02 15:29:47 +00:00
Samuel Pitoiset
427fd83d27 radv: use new EVENT_WRITE_ZPASS packet3 on GFX11 
Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21621>
 2023-03-02 12:53:27 +00:00
Samuel Pitoiset
87444bb7ab radv: ignore alpha_is_on_msb on GFX11 because the hw ignores it 
Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21621>
 2023-03-02 12:53:27 +00:00
Georg Lehmann
ede0630f9e aco: use v_fma_mix_f32 for v_fma_f32 with 2 fp16 representable, different literals 
We can pack two fp16 literals into one 32bit literal and use opsel to select
the correct value. Note that LLVM currently disassembles these instructions
incorrectly.

Foz-DB Navi21:
Totals from 13365 (9.91% of 134913) affected shaders:
VGPRs: 840880 -> 840016 (-0.10%); split: -0.11%, +0.01%
SpillSGPRs: 724 -> 722 (-0.28%)
CodeSize: 82439364 -> 82451336 (+0.01%); split: -0.06%, +0.08%
MaxWaves: 244858 -> 244980 (+0.05%)
Instrs: 15265976 -> 15247201 (-0.12%); split: -0.13%, +0.01%
Latency: 223316180 -> 223272495 (-0.02%); split: -0.03%, +0.02%
InvThroughput: 41981375 -> 41969917 (-0.03%); split: -0.04%, +0.01%
VClause: 266775 -> 266558 (-0.08%); split: -0.14%, +0.06%
SClause: 646602 -> 645996 (-0.09%); split: -0.16%, +0.07%
Copies: 794703 -> 776075 (-2.34%); split: -2.46%, +0.12%
Branches: 296317 -> 296316 (-0.00%)
PreSGPRs: 658796 -> 656479 (-0.35%); split: -0.35%, +0.00%
PreVGPRs: 744014 -> 743679 (-0.05%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20587>
 2023-03-02 10:59:05 +00:00
Georg Lehmann
ed349951cb aco: mark mad definition as precise if the mul/add were precise 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20587>
 2023-03-02 10:59:05 +00:00
Samuel Pitoiset
f19fccd9f8 amd,ac/rgp: fix SQTT memory types 
This crashed on Steam Deck because the memory type is LPDDR5 and it
wasn't not handled in the switch. It seems the kernel changed the
memory type returned for VanGogh because it used to work.

Fixes: aef7ea868f ("ac/gpu_info: handle LPDDR4 and 5 in ac_memory_ops_per_clock")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21627>
 2023-03-02 07:54:35 +00:00
Chia-I Wu
e2c67ed63e ci/radv: remove dEQP-VK.image.sample_texture.* fails/flakes 
They were fixed since commit 11b2a063bf ("vulkan: Unconditionally add
barriers for missing external subpass deps").

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21616>
 2023-03-02 00:56:16 +00:00
Samuel Pitoiset
3ced4ae816 radv: only expose EXT_pipeline_library_group_handles if RT is enabled 
VK_EXT_pipeline_library_group_handles requires
VK_KHR_ray_tracing_pipeline to be enabled.

Fixes dEQP-VK.info.device_extensions.

Fixes: ed76833705 ("radv: Implement & expose VK_EXT_pipeline_library_group_handles.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21618>
 2023-03-01 10:55:00 +00:00
Dave Airlie
24c09d4b16 radv: add video format support to format probing. 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21457>
 2023-03-01 07:16:47 +00:00
Tatsuyuki Ishi
bab235106e radv: Replace radv_trap_handler_shader with radv_shader. 
Now that the upload memory is tied to the shader itself, the trap handler
shader no longer needs an additional wrapper.

This is a cleanup to ease introduction of a new shader uploading code path.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21541>
 2023-03-01 05:12:10 +00:00
Konstantin Seurer
5ce99bc568 radv: Only init geometry infos if RRA is enabled 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21532>
 2023-02-28 20:49:33 +00:00
Konstantin Seurer
7bd265bc86 radv: Move header and geometry info init into separate functions 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21532>
 2023-02-28 20:49:33 +00:00
Samuel Pitoiset
c356f1b4ed radv: fix draw calls with 0-sized index buffers and robustness on NAVI10 
The correct workaround is to bind an internal index buffer to handle
robustness2 correctly.

Fixes dEQP-VK.robustness.index_access.* in CTS 1.3.5.0 on NAVI10.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21471>
 2023-02-28 14:12:29 +00:00
Samuel Pitoiset
7c62f6fa01 radv: fix flushing non-coherent images in EndCommandBuffer() 
The condition was inverted.

This doesn't fix anything known.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21549>
 2023-02-28 09:35:07 +00:00
Samuel Pitoiset
6750a9094f radv: fix flushing non-coherent images inside secondaries on GFX9+ 
Fixes
dEQP-VK.draw.dynamic_rendering.complete_secondary_cmd_buff.multi_draw.mosaic.*
on VEGA10 (related to the use of HTILE).

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21549>
 2023-02-28 09:35:07 +00:00
Qiang Yu
4b3a22fcd4 aco: only ls and ps use store output now 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21435>
 2023-02-28 07:19:29 +00:00
Qiang Yu
e9616d1d2a ac/llvm: only init outputs when fragment shader for radv 
LS pass output to TCS by reg is not enabled when LLVM.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21435>
 2023-02-28 07:19:29 +00:00
Georg Lehmann
e1eabab6fe aco/optimizer_postRA: assume all registers are untrackable in loop headers 
Register writes from the pre-header might not be correct for any but
the first loop iteration because they can be clobbered inside the loop.

Foz-DB Navi21:
Totals from 18 (0.01% of 134913) affected shaders:
CodeSize: 251384 -> 251508 (+0.05%)
Instrs: 47644 -> 47664 (+0.04%)
Latency: 801801 -> 801852 (+0.01%)
InvThroughput: 177579 -> 177593 (+0.01%)
Copies: 4752 -> 4771 (+0.40%)

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8376
Fixes: d3b0f78110 ("aco/optimizer_postRA: Initialize loop header with preheader information")

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21540>
 2023-02-28 04:27:05 +00:00
Emma Anholt
fef6e6588b ci: Update traces expectations for gutting glsl opt_algebraic. 
All look like harmless changes.

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21475>
 2023-02-28 03:36:09 +00:00
Rhys Perry
75d9a4a6ce aco: always update orig_names in get_reg_phi() 
No idea why this wasn't done if pc.first was a renamed temporary.

Fixes navi10 RA validation error with
dEQP-VK.binding_model.descriptor_buffer.multiple.graphics_geom_buffers1_sets3_imm_samplers

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8349
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21501>
 2023-02-27 15:10:22 +00:00
Eric Engestrom
735df516e9 radv: split linker script for android since it requires different symbols 
Fixes: 4956f6d0bf ("radv: Add Android module info to linker script.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8338
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21518>
 2023-02-27 14:34:16 +00:00
Mike Blumenkrantz
7c8a5f6e37 vulkan/wsi: switch to using an options struct for last param 
this makes adding values easier since the drivers won't need to be updated

Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21447>
 2023-02-27 13:21:21 +00:00
Georg Lehmann
1c5c2f77c3 aco: use and swizzle mask in dpp quad perm 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21412>
 2023-02-27 11:09:42 +00:00
Georg Lehmann
8fabde3be4 aco/gfx11: use dpp_row_xmask and dpp_row_share 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21412>
 2023-02-27 11:09:42 +00:00
Georg Lehmann
b7cd0eb439 aco: use v_permlane(x)16_b32 for masked swizzle 
Should be cheaper than ds_swizzle.

Totals from 8 (0.01% of 134913) affected shaders:
CodeSize: 16316 -> 16388 (+0.44%)
Instrs: 3088 -> 3086 (-0.06%)
Latency: 49558 -> 49508 (-0.10%)
InvThroughput: 9180 -> 9198 (+0.20%)
Copies: 376 -> 384 (+2.13%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21412>
 2023-02-27 11:09:42 +00:00
Georg Lehmann
9f155c21c3 amd: d16 uses rtz conversion for 32bit float 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21404>
 2023-02-27 09:55:34 +00:00
Georg Lehmann
77252687fa amd: don't use d16 for integer loads 
D16 saturates to min/max instead of just truncating.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21404>
 2023-02-27 09:55:34 +00:00
Georg Lehmann
a00b50d820 nir: change 16bit image dest folding option to per type 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21404>
 2023-02-27 09:55:34 +00:00
Samuel Pitoiset
a14d46fde2 radv: enable primitiveUnderestimation on GFX9+ 
It's passing dEQP-VK.rasterization.conservative.underestimate.* on
NAVI21.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21459>
 2023-02-27 09:04:01 +00:00
Samuel Pitoiset
dba7a66429 radv: set MSAA_NUM_SAMPLES to 0 for underestimate rasterization 
Based on PAL.

Fixes
dEQP-VK.rasterization.conservative.underestimate.samples_*.triangles.normal.test.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21459>
 2023-02-27 09:04:01 +00:00
Samuel Pitoiset
0eae617826 radv: stop setting ENABLE_POSTZ_OVERRASTERIZATION to 1 
According to PAL this isn't set.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21459>
 2023-02-27 09:04:01 +00:00
Samuel Pitoiset
05732f4519 radv: cleanup radv_emit_{conservative,msaa}_state() functions 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21459>
 2023-02-27 09:04:01 +00:00
Tatsuyuki Ishi
ed03821442 radv/sqtt: Use code buffer from radv_shader directly instead of copying. 
The reference-counted radv_shader always outlives the pipeline, so we can
use this buffer directly when dumping code objects to the trace.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21513>
 2023-02-27 07:16:48 +00:00
Tatsuyuki Ishi
ea070fb83a radv: Keep shader code ptr in a separately allocated buffer. 
RGP traces need a dump of shader code in order to display ISA and
instruction trace. Previously, this was read back from GPU at trace
creation time. However, for future changes that implements upload shader
to invisible VRAM, the upload destination will be a temporary staging
buffer and will be only accessible during shader creation.

To allow dumping in such cases, copy the shader code to a separate buffer
at creation time, if thread tracing is enabled.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21513>
 2023-02-27 07:16:48 +00:00
Qiang Yu
822e756511 ac/llvm,radeonsi: lower fbfetch in abi 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21436>
 2023-02-27 09:43:53 +08:00
Qiang Yu
5c44404b5f ac/llvm,radeonsi: lower nir_load_barycentric_at_sample in abi 
RADV already did this in radv_lower_fs_intrinsics().

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21436>
 2023-02-27 09:39:41 +08:00
Konstantin Seurer
2d93ab795b radv/rt: Pre shift cull_mask 
This removes the need for masking the instance mask.

Totals from 14 (14.43% of 97) affected shaders:
CodeSize: 378696 -> 378308 (-0.10%); split: -0.12%, +0.02%
Instrs: 70854 -> 70855 (+0.00%); split: -0.02%, +0.02%
Latency: 1651235 -> 1651215 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 336290 -> 336285 (-0.00%); split: -0.00%, +0.00%
Copies: 9915 -> 9923 (+0.08%); split: -0.03%, +0.11%
PreSGPRs: 890 -> 896 (+0.67%)

 PERCENTAGE DELTAS Shaders  CodeSize   Instrs   Latency  InvThroughput   Copies   PreSGPRs
 q2rtx-pipe        48        -0.02%    -0.02%    -0.00%      -0.00%      -0.03%      .
 q2rtx_1           49        -0.10%    +0.02%    +0.00%      +0.00%      +0.14%    +0.31%
 -------------------------------------------------------------------------------------------
 All affected      14        -0.10%    +0.00%    -0.00%      -0.00%      +0.08%    +0.67%
 -------------------------------------------------------------------------------------------
 Total             97        -0.06%    +0.00%    -0.00%      -0.00%      +0.06%    +0.16%

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21530>
 2023-02-26 12:58:13 +00:00
Konstantin Seurer
13a9ce7f2f radv/rt: Merge cull_mask and flags 
Since cull_mask is only one byte, we can trivially store it in the same
register as the flags. This leaves us with a 2% performance gain in
Quake II RTX:

Totals from 7 (14.00% of 50) affected shaders:
VGPRs: 720 -> 688 (-4.44%)
CodeSize: 213052 -> 212980 (-0.03%); split: -0.05%, +0.02%
MaxWaves: 67 -> 70 (+4.48%)
Instrs: 39429 -> 39394 (-0.09%); split: -0.15%, +0.06%
Latency: 1096258 -> 1096943 (+0.06%); split: -0.05%, +0.11%
InvThroughput: 230661 -> 222963 (-3.34%); split: -3.42%, +0.08%
VClause: 1208 -> 1206 (-0.17%); split: -0.25%, +0.08%
Copies: 5321 -> 5269 (-0.98%); split: -1.22%, +0.24%
Branches: 1903 -> 1902 (-0.05%)
PreVGPRs: 650 -> 645 (-0.77%)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21470>
 2023-02-25 12:07:46 +00:00
Marek Olšák
9f1e6d8f70 nir,amd: add and use nir_intrinsic_load_esgs_vertex_stride_amd 
This will emulate VGT_ESGS_RING_ITEMSIZE, which does the multiplication
for us. It's beneficial to stop setting VGT_ESGS_RING_ITEMSIZE to reduce
context rolls, and also the register will be removed in the future.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
 2023-02-24 21:27:24 +00:00
Marek Olšák
5e837f9594 amd/gpu_info: add a workaround for SI_FORCE_FAMILY=gfx1100 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
 2023-02-24 21:27:24 +00:00
Marek Olšák
df6380ddc9 amd: implement conformant TRUNC_COORD behavior for gfx11 
For testing, the conformant behavior can be enabled by setting
conformant_trunc_coord to true manually and running this to enable
the conformant behavior in hw:
    umr -w *.*.regTA_CNTL2 0x40000

The layer index rounding and TRUNC_COORD resetting workarounds can disabled
in the shader compiler.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
 2023-02-24 21:27:24 +00:00
Marek Olšák
3e8bd05020 radeonsi: don't set PACKET_TO_ONE_PA for line stippling 
A hw guy told me this.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
 2023-02-24 21:27:24 +00:00