Commit graph

82384 commits

Author SHA1 Message Date
Jason Ekstrand
2d2c6fc6bb anv/wsi/wayland: Advertise sRGB 2016-02-01 13:06:35 -08:00
Jason Ekstrand
443c578bca anv/wsi/x11: Expose SRGB all the time
After a long discussion with Eric Anholt and Owen Taylor, I learned that
X11 is basically always sRGB as that's what the scanout hardware does and X
doesn't modify anything.  Therefore, we should just always expose sRGB
formats.
2016-02-01 13:06:35 -08:00
Chad Versace
afb327a985 anv: Structify a one-member union
anv_descriptor contained a union with one member.
2016-02-01 12:18:10 -08:00
Kristian Høgsberg Kristensen
dc5fdcd6b7 anv: Advertise robustBufferAccess
The GPU does most of this for us as long as we set up tight bounds for
the buffers, which we do. Additionally, we range check dynamically
buffers in the shader. With that it's safe to turn on robustBufferAccess.
2016-02-01 12:00:05 -08:00
Chad Versace
ffbc32f8d9 anv/meta: Strip trailing whitespace 2016-02-01 10:51:01 -08:00
Chad Versace
aa5e257860 anv: Update MSAA status in README 2016-02-01 10:46:24 -08:00
Matt Turner
75c9def8ee i965/gen7+: Use NIR for lowering of pack/unpack opcodes.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00
Matt Turner
f4952421cd i965/vec4: Implement nir_op_pack_uvec2_to_uint.
And mark nir_op_pack_uvec4_to_uint unreachable, since it's only produced
by lowering pack[SU]norm4x8 which the vec4 backend does not need.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00
Matt Turner
955d052058 nir: Add lowering support for unpacking opcodes.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00
Matt Turner
9b8786eba9 nir: Add lowering support for packing opcodes.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00
Matt Turner
1dc312e295 i965/fs: Implement support for extract_word.
The vec4 backend will lower it.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00
Matt Turner
68f8c5730b nir: Add opcodes to extract bytes or words.
The uint versions zero extend while the int versions sign extend.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00
Matt Turner
8709dc0713 glsl: Remove 2x16 half-precision pack/unpack opcodes.
i965/fs was the only consumer, and we're now doing the lowering in NIR.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00
Matt Turner
1a53a4fc7a i965/fs: Switch from GLSL IR to NIR for un/packHalf2x16 scalarizing.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00
Matt Turner
9ce901058f nir: Add lowering of nir_op_unpack_half_2x16.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00
Matt Turner
e4278a847e i965: Make separate nir_options for scalar/vector stages.
We'll want to have different lowering options set for scalar/vector
stages.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00
Matt Turner
252d497d4c i965: Move brw_compiler_create() to new brw_compiler.c.
A future patch will want to use designated initalizers, which aren't
available in C++, but this is C.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00
Matt Turner
140a886c41 nir: Make argument order of unop_convert match binop_convert.
Strangely the return and parameter types were reversed.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-01 10:43:57 -08:00
Jason Ekstrand
a88b1eeb13 Update the README 2016-02-01 06:10:51 -08:00
Jason Ekstrand
ea63663a72 wsi/x11: Remove B8G8R8_UNORM
We don't actually support that format yet because ISL doesn't have an enum
for it.  We need to beef up the formats table to allow for tiled-only
formats.
2016-02-01 06:00:50 -08:00
Marta Lofstedt
77a60ab5dc mesa: enable enums for OES_geometry_shader
Enable GL_OES_geometry_shader enums for OpenGL ES 3.1.

V4: EXTRA tokens updated according to comments from Ilia Mirkin.

V5: Account for check_extra does not evaluate "or" lazy. Fix issues
with EXTRA_EXT_FB_NO_ATTACH_CS.

Signed-off-by: Marta Lofstedt <marta.lofstedt@linux.intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-01 09:30:50 +01:00
François Tigeot
a48afb92ff gallium: Add DragonFly support
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-01-31 11:56:09 +00:00
Jordan Justen
f96a6c65a3 anv/gen7: Rename gen7_batch_lr* to emit_lr*
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-01-30 15:06:03 -08:00
Jordan Justen
b207a6b5aa anv/gen7: Set BypassGatewayControl in MEDIA_VFE_STATE
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-01-30 15:06:03 -08:00
Ilia Mirkin
7f19e29305 nv50/ir: get rid of memory stores with nop values
This happens especially with exports and varying packing, where the last
bits aren't always filled in. We end up trying to do quad-wide stores,
which ends up being a lot of register moves that carefully preserve the
nop value. Instead don't do the stores.

total instructions in shared programs : 6131375 -> 6125267 (-0.10%)
total gprs used in shared programs    : 910139 -> 895501 (-1.61%)
total local used in shared programs   : 15328 -> 15328 (0.00%)

                local        gpr       inst
    helped           0        7442        4693
      hurt           0          90        2687

Most of the helped/hurt instruction changes are by one or two ops
because can no longer do quad-wide stores in all cases.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-30 17:18:41 -05:00
Ilia Mirkin
3ca941d60e nv50/ir: fix false global CSE on instructions with multiple defs
If an instruction has multiple defs, we have to do a lot more checks to
make sure that we can move it forward. Among other things, various code
likes to do

    a, b = tex()
    if () c = a
    else c = b

which means that a single phi node will have results pointing at the
same instruction. We obviously can't propagate the tex in this case, but
properly accounting for this situation is tricky. Just don't try for
instructions with multiple defs.

This fixes about 20 shaders in shader-db, including the dolphin efb2ram
shader.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2016-01-30 17:18:41 -05:00
Ilia Mirkin
3ca2001b53 nv50,nvc0: fix buffer clearing to respect engine alignment requirements
It appears that the nvidia render engine is quite picky when it comes to
linear surfaces. It doesn't like non-256-byte aligned offsets, and
apparently doesn't even do non-256-byte strides.

This makes arb_clear_buffer_object-unaligned pass on both nv50 and nvc0.

As a side-effect this also allows RGB32 clears to work via GPU data
upload instead of synchronizing the buffer to the CPU (nvc0 only).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> # tested on GF108, GT215
Tested-by: Nick Sarnie <commendsarnex@gmail.com> # GK208
Cc: mesa-stable@lists.freedesktop.org
2016-01-30 16:01:41 -05:00
Jordan Justen
2d8726a4b7 anv/genX_pipeline: Remove unnecessary #include files
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-01-30 09:30:54 -08:00
Rob Clark
f15447e7c9 freedreno/ir3: ignore clip-vertex varying
Since we emulate clip-planes, the clip-vertex is used within the VS
itself (thanks to nir_lower_clip).  So just ignore it as a VS output.
Fixes a boatload of piglit tests that were asserting on unknown
varying slot.

(Also unrelated spelling/typo fix.)

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-01-30 12:29:21 -05:00
Rob Clark
f20cf22b54 freedreno/ir3: don't ignore local vars
With glsl_to_nir we end up with local variables, instead of global, for
arrays.

Note that we'll eventually have to do something more clever, I think,
when we support multiple functions, but that will probably take some
work in a few places.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-01-30 12:27:57 -05:00
Rob Clark
8039a2a6b3 freedreno/ir3: handle tex instrs w/ const offset
Something we start to see with glsl_to_nir.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-01-30 12:27:27 -05:00
Rob Clark
f212d7dc50 freedreno/ir3: support load_front_face intrinsic
With tgsi_to_nir we get this as a normal input with VARYING_SLOT_FACE.
But glsl_to_nir plus nir_lower_system_values this becomes an intrinsic.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-01-30 12:11:54 -05:00
Jordan Justen
8e48ff3ad6 anv/gen7: Set SLM size in interface descriptor
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-01-30 09:10:54 -08:00
Rob Clark
9e05e8cb75 freedreno: limit string marker to max packet size
Experimentally derived max size.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-01-30 12:10:13 -05:00
Jordan Justen
ab0d8608d2 anv: Support MEDIA_VFE_STATE for gen7
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-01-30 09:08:34 -08:00
Jordan Justen
dd2effb0e7 anv/gen7: Subtract 1 from num_elements when setting up buffer surface state
e8f51fe4 for gen7

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-01-30 09:00:00 -08:00
Jordan Justen
4bb1e7937a anv/gen7: Disable fs dispatch for depth/stencil only pipelines
292031a for gen7

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-01-30 09:00:00 -08:00
Jordan Justen
f5b3a2fe32 anv/gen7: Add support for gl_NumWorkGroups
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-01-30 09:00:00 -08:00
Jordan Justen
7e46cc8603 anv/gen7/compute: Setup push constants and local ids
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-01-30 09:00:00 -08:00
Jordan Justen
b1158ced45 anv/genX: Add genX_pipeline.c for compute_pipeline_create
Adds initial compute_pipeline_create implementation for gen7.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-01-30 08:58:11 -08:00
Jason Ekstrand
1a442a7923 Merge branch 'vulkan' into 'vulkan'
Vulkan WSI Wayland fixes

Two small fixes to make mailbox mode actually work again.

See merge request !4
2016-01-30 10:28:12 -05:00
Jason Ekstrand
c668dc9f75 anv/pass: Initialize has_resolve 2016-01-30 07:16:33 -08:00
Jason Ekstrand
ad813b072a anv/wsi: Set the platform field of VkIcdSurfaceBase 2016-01-30 07:05:53 -08:00
Jason Ekstrand
5acc4e2ebf anv/wsi/x11: Actually pull information from the window's visual 2016-01-30 03:51:47 -08:00
Jason Ekstrand
66e8b5cf2b anv/wsi/x11: Actually check for DRI3 2016-01-30 03:50:31 -08:00
Jason Ekstrand
44ec860cd6 anv/WSI: Support more usage bits
They're just images and we have no intention of stompping alpha channels
(at least not yet), so there's no reason why you can't sample.
2016-01-29 20:52:44 -08:00
Jason Ekstrand
337c1e0871 anv/formats: Add more compressed formats
This adds support for the DX compression formats.  Given that ETC and EAC
are working fine, these should be ok too.
2016-01-29 20:46:31 -08:00
Jason Ekstrand
c688e4db11 anv/wsi: Rework to be compatable with the loader 2016-01-29 20:39:21 -08:00
Jason Ekstrand
d4953fb340 vulkan: Import vk_icd.h 2016-01-29 20:37:45 -08:00
Jason Ekstrand
a19ceee46c anv/device: Fix version check
The bottom-end check was wrong so it was only working on <= 1.0.0.  Oops.
2016-01-29 20:36:58 -08:00