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Author SHA1 Message Date
Georg Lehmann
293d2e3b0d nir/algebraic: remove ability to create Value from Expression 
Not used, and it would break in the future.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39616>
 2026-01-31 15:30:25 +00:00
Georg Lehmann
ad6f8291bf nir/opt_algebraic: rework ignore_exact to work like other internal conditions 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39616>
 2026-01-31 15:30:25 +00:00
Georg Lehmann
a879b9a5d5 nir/search: preserve nan/inf/sz if any alu in a replaced expression did 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39616>
 2026-01-31 15:30:25 +00:00
Georg Lehmann
575affaf48 nir/search: gather union of all fp_math_ctrl 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39616>
 2026-01-31 15:30:25 +00:00
Karol Herbst
dc03f94e07 clc: fix compile compatability with LLVM-22
Some checks are pending
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Details 
See d090311aa7

Cc: mesa-stable
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39374>
 2026-01-30 16:06:26 +00:00
Karol Herbst
24d20df3d6 nir: fix nir_fixup_is_exported for LLVM-22 
Starting with LLVM-22 we won't see the kernel wrapper anymore, and this
is a trivial fix to get around this.

See: 5458eb2511

Cc: mesa-stable
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39374>
 2026-01-30 16:06:25 +00:00
Karol Herbst
6eda573a8a clc: enable generic address space and seq_cst and device scope atomic features 
This is going to be required with LLVM-22.

See 423bdb2bf2

Cc: mesa-stable
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39374>
 2026-01-30 16:06:25 +00:00
Karol Herbst
01e1392139 clc: support some atomic and generic address space features 
Cc: mesa-stable
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39374>
 2026-01-30 16:06:25 +00:00
Karol Herbst
7f9a7ed553 clc: reorder headers to fix compilation errors due to UNUSED 
Cc: mesa-stable
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39374>
 2026-01-30 16:06:25 +00:00
Georg Lehmann
70f0e75262 nir/opt_algebraic: optimize pack_half_2x16_rtz of float converted from 16bit 
Foz-DB Navi48:
Totals from 177 (0.21% of 82405) affected shaders:
Instrs: 326628 -> 325955 (-0.21%); split: -0.21%, +0.00%
CodeSize: 1726720 -> 1722500 (-0.24%); split: -0.24%, +0.00%
Latency: 5076631 -> 5075700 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 596010 -> 595598 (-0.07%); split: -0.07%, +0.00%
VClause: 3613 -> 3616 (+0.08%)
Copies: 24427 -> 24501 (+0.30%); split: -0.06%, +0.36%
VALU: 182468 -> 182029 (-0.24%); split: -0.24%, +0.00%
SALU: 55449 -> 55452 (+0.01%); split: -0.01%, +0.01%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39531>
 2026-01-29 14:44:37 +00:00
Georg Lehmann
c3e12429c5 nir/opt_algebaric: improve a < 0.0 ? 0.0 : sqrt(a) pattern 
Fix the NaN correctness of the original pattern, and add more variants.

Foz-DB Navi48:
Totals from 372 (0.45% of 82405) affected shaders:
Instrs: 208946 -> 207522 (-0.68%); split: -0.71%, +0.03%
CodeSize: 1116436 -> 1109804 (-0.59%); split: -0.61%, +0.02%
VGPRs: 19452 -> 19104 (-1.79%)
Latency: 1121222 -> 1120423 (-0.07%); split: -0.13%, +0.05%
InvThroughput: 158228 -> 157567 (-0.42%); split: -0.61%, +0.19%
VClause: 3695 -> 3704 (+0.24%)
Copies: 9516 -> 9606 (+0.95%); split: -0.24%, +1.19%
VALU: 118696 -> 118031 (-0.56%); split: -0.61%, +0.05%
VOPD: 380 -> 372 (-2.11%)

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39507>
 2026-01-29 11:29:48 +00:00
Georg Lehmann
f872c13707 nir/opt_algebraic: use contract instead of inexact for more patterns 
These use more precise operations, so contract is enough.

Foz-DB Navi48:
Totals from 248 (0.30% of 82405) affected shaders:
Instrs: 284686 -> 284318 (-0.13%); split: -0.14%, +0.01%
CodeSize: 1528856 -> 1527520 (-0.09%); split: -0.10%, +0.01%
Latency: 2368390 -> 2367345 (-0.04%); split: -0.06%, +0.01%
InvThroughput: 346623 -> 346335 (-0.08%); split: -0.09%, +0.01%
SClause: 6752 -> 6756 (+0.06%); split: -0.12%, +0.18%
Copies: 14685 -> 14694 (+0.06%); split: -0.01%, +0.07%
VALU: 179922 -> 179727 (-0.11%); split: -0.11%, +0.01%
SALU: 28706 -> 28707 (+0.00%)
VOPD: 1196 -> 1198 (+0.17%)

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39507>
 2026-01-29 11:29:48 +00:00
Georg Lehmann
f472bbf017 nir/algebraic: remove manual opcode validation
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The properly terminated regex automatically detects this case now.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39586>
 2026-01-28 18:46:23 +00:00
Georg Lehmann
a5f55be021 nir/algebraic: terminate opcode regex 
Instead of silently dropping the unmatched rest.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39586>
 2026-01-28 18:46:23 +00:00
Georg Lehmann
d8ef28671d nir/opt_algebraic: use correct syntax to create exact fsat 
Fixes: 3b06824e4c ("nir/opt_algebraic: optimize some post peephole select patterns")

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39586>
 2026-01-28 18:46:22 +00:00
Georg Lehmann
1240444e63 spirv: assert fp_math_ctrl was reset after use 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39460>
 2026-01-27 23:01:44 +00:00
Georg Lehmann
3deb57b654 spirv: remove vtn_builder::exact 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39460>
 2026-01-27 23:01:44 +00:00
Georg Lehmann
51d30d0f96 spirv: consider both source and dest type for fast math 
This matters for conversions and and comparisons.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39460>
 2026-01-27 23:01:44 +00:00
Georg Lehmann
46a617884e spirv: use base type instead of bit size to determine fp_math_ctrl 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39460>
 2026-01-27 23:01:44 +00:00
Georg Lehmann
565f37b98c spirv: handle fast_math for opencl opcodes 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39460>
 2026-01-27 23:01:42 +00:00
Georg Lehmann
836efa8c3c spirv: move NoContraction handling into vtn_handle_fp_fast_math 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39460>
 2026-01-27 23:01:42 +00:00
Iván Briano
5b48805b42 brw: fix local_invocation_index with quad derivaties on mesh/task shaders 
For mesh/task shaders, the thread payload provides a local invocation
index, but it's always linear so it doesn't give the correct value when
quad derivatives are in use.
The lowering pass where all of this is done correctly for compute
shaders assumes load_local_invocation_index will be lowered in the
backend for mesh/task, calculates the values for the quads correctly but
then avoid replacing the original intrinsic and we remain with the wrong
results.

Add an intel specific intrinsic and always lower the generic one to that
(or whatever else was calculated) to avoid ambiguities and fix the value
for quad derivatives.

Fixes future CTS tests using mesh/task shaders under:
dEQP-VK.spirv_assembly.instruction.compute.compute_shader_derivatives.*

Fixes: d89bfb1ff7 ("intel/brw: Reorganize lowering of LocalID/Index to handle Mesh/Task")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39276>
 2026-01-27 22:28:19 +00:00
Emma Anholt
eb990cd81e nir: Bump test timeouts. 
nir_opt_algebraic_tests has been pushing our qemu-ed tests over the line.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39563>
 2026-01-27 21:31:14 +00:00
Eric Engestrom
d12e3454e6 nir/meson: fix cpp_args of nir_opt_algebraic_pattern_tests 
Fixes: 4c30c44b75 ("nir: Generate unit tests for nir_opt_algebraic")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39550>
 2026-01-27 20:03:16 +00:00
Kenneth Graunke
b844082017 nir: Add a round_up_components callback to load/store vectorization 
By default, load/store vectorization uses nir_round_up_components()
to round up loads and possibly writemasked stores to the next valid
NIR vector width.  However, some backends may not support load/stores
at all sizes.  For example, older Intel supports only power-of-two
vector widths.  Newer Intel also supports vec2 and vec3, but not
vec5/6/7.  By providing a callback, backends can request promotion
to their next supported memory load/store vector width.

The existing "should we vectorize?" callback should continue to return
false for unsupported vector widths (i.e. beyond the maximum supported).
With this new callback, they do not need to say "no" to vectorization
that would normally produce an unsupported count (e.g. vec5/6/7) but
instead request that the component count be rounded up appropriately.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39250>
 2026-01-27 16:08:36 +00:00
Kenneth Graunke
e23a83b786 nir: Add load/store vectorizer option for rounding up masked stores 
This adds a new option, round_up_store_components, which rounds up the
number of components for stores that support writemasking to the next
valid vector size.  For example, vec4+vec2 stores would round up from
6 components (which wouldn't be supported) to a full supportable vec8
store, relying on writemasking to ensure the correct pieces are written.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39250>
 2026-01-27 16:08:36 +00:00
Kenneth Graunke
37f3c59b2c nir: Teach opt_load_store_vectorize how to handle Intel URB intrinsics 
URB intrinsics are simply memory load/stores to a special memory region,
so it's pretty reasonable to handle these in the memory vectorizer.  We
treat emit_vertex_* intrinsics as a barrier for shader outputs.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39250>
 2026-01-27 16:08:36 +00:00
Kenneth Graunke
c2f03ba12f nir: Add memory modes to URB load intrinsics 
This makes it easier for NIR passes to distinguish between inputs and
outputs without having to reason about which URB handle source was
passed to the intrinsic.  It probably also makes it a bit easier for
humans to read the NIR too.

v2: Don't add memory mode to store intrinsics.  It's always output.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39250>
 2026-01-27 16:08:36 +00:00
Emma Anholt
e922c2cabc nir,spirv: Add support for SPV_QCOM_image_processing. 
Initial work was done by Mark Collins, which I significantly rewrote.

Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38559>
 2026-01-27 02:00:40 +00:00
Emma Anholt
f289c460eb isaspec: Print the bit number when just a single bit is undefined. 
I'm tired of counting my bits by hand.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38559>
 2026-01-27 02:00:40 +00:00
Emma Anholt
8a2a14a31a isaspec: Print the bitset we're processing when missing a field. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38559>
 2026-01-27 02:00:40 +00:00
Emma Anholt
3d8cfa77d7 isaspec: Improve debug info for extractor_fallback(). 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38559>
 2026-01-27 02:00:39 +00:00
Emma Anholt
e8e6e42e71 isaspec: Print a useful error for an assert I hit. 
Trying to write new isaspec xml makes me wish for rust's anyhow crate.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38559>
 2026-01-27 02:00:39 +00:00
Dave Airlie
6d53931cf4 nir: add cmat call to propogate invariants 
This just adds this as lavapipe uses this pass.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38964>
 2026-01-26 22:39:40 +00:00
Daniel Schürmann
6313e9f549 nir/opt_loop: Relax restrictions on opt_loop_peel_initial_break() for more loops 
In addition to loops where the break condition can be constant-folded,
we also allow to peel the initial break from loops which have at least
one phi with a constant loop-carried source, effectively removing that
phi from the loop.

Totals from 172 (0.22% of 79377) affected shaders: (Navi31)
Instrs: 372798 -> 369181 (-0.97%); split: -1.07%, +0.10%
CodeSize: 1907312 -> 1891948 (-0.81%); split: -0.89%, +0.09%
VGPRs: 8436 -> 8460 (+0.28%)
Latency: 3646016 -> 3396657 (-6.84%)
InvThroughput: 434848 -> 389079 (-10.53%)
Copies: 28436 -> 27118 (-4.63%); split: -4.79%, +0.15%
Branches: 26504 -> 25344 (-4.38%); split: -4.44%, +0.06%
PreSGPRs: 8585 -> 8603 (+0.21%)
VALU: 148291 -> 148355 (+0.04%); split: -0.01%, +0.06%
SALU: 95625 -> 92649 (-3.11%); split: -3.22%, +0.11%

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33666>
 2026-01-26 12:02:49 +00:00
Georg Lehmann
b2d9615000 nir/opt_algebraic: optimize bcsel to hi 16bits with undef lo 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39412>
 2026-01-26 10:54:20 +00:00
Georg Lehmann
d06b627d23 nir/opt_algebraic: optimize f2f16_rtz of bcsel with constants 
Foz-DB Navi48:
Totals from 145 (0.18% of 82405) affected shaders:
Instrs: 1706001 -> 1705669 (-0.02%); split: -0.03%, +0.01%
CodeSize: 9621036 -> 9620784 (-0.00%); split: -0.02%, +0.02%
SpillSGPRs: 711 -> 726 (+2.11%); split: -0.56%, +2.67%
Latency: 20066360 -> 20066193 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 4326789 -> 4326763 (-0.00%); split: -0.00%, +0.00%
Copies: 192041 -> 191995 (-0.02%); split: -0.03%, +0.01%
Branches: 75673 -> 75675 (+0.00%); split: -0.00%, +0.01%
VALU: 765163 -> 764835 (-0.04%); split: -0.05%, +0.00%
SALU: 351758 -> 351715 (-0.01%); split: -0.01%, +0.00%
VOPD: 65236 -> 65282 (+0.07%); split: +0.17%, -0.10%

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39412>
 2026-01-26 10:54:20 +00:00
Georg Lehmann
ee5492e6dd nir/opt_algebraic: remove f2f16 roundtrip conversions 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39412>
 2026-01-26 10:54:20 +00:00
Georg Lehmann
592b6579da nir/opt_algebraic: optimize f2f16_rtz(min/max) 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39412>
 2026-01-26 10:54:18 +00:00
Georg Lehmann
2b92c0f06e nir/opt_algebraic: optimize f2f16_rtz(b2f(a)) 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39412>
 2026-01-26 10:54:18 +00:00
Emma Anholt
feb3e8f46e nir/opt_algebraic_tests: Initialize an obvious dummy value for all defs.
Some checks are pending
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We were initializing to a nir_const_value of undefined (in practice on x86
builds, a pointer value), with .b set to 0.  Those values would get dumped
in the annotated shader disassembly at the end of a test where all inputs
where unexpectedly skipped, producing very surprising output.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:42 +00:00
Emma Anholt
6b6cf7b89f nir/opt_algebraic_tests: Fix annotating uint values. 
In debugging the CI flakes, it was disconcerting to see:

1     %1 = fisnormal %0 (0.000000) // 0x55e7c4147c00

instead of:

1     %1 = fisnormal %0 (0.000000) // 0x0

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:42 +00:00
Emma Anholt
77cfb20d0a nir/opt_algebraic_tests: Fix leak of the variable conds ht. 
We'd end the test with 500MB leaked.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:42 +00:00
Emma Anholt
cdec063d37 nir/opt_algebraic: Fix a bit of imad24_ir3's optimization. 
The mul is 24-bit sign-extended, so in simplifying we should retain that.
If nothing else, this keeps us on the happy path of mul24s.

I didn't fix the other broken pattern, since it's not really part of this
MR.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:41 +00:00
Emma Anholt
e5a9eae2b5 nir/opt_algebraic_tests: Fix fuzzing levels for multi-component inputs. 
We were enumerating enough for a single component, but not all the
combinations.  This helps show that our fdots fail pretty consistently.
And triggers more skipping from the fany_equal16s thanks to varied inputs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:41 +00:00
Emma Anholt
7fd0287a89 nir/opt_algebraic_tests: Test !nir_fp_preserve_signed_zero behavior. 
Iterate over a set of sign-flips for 0.0s to see if we can find a set that
makes the search and replace sides match.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:41 +00:00
Emma Anholt
d9eb9a3eef nir/opt_algebraic_tests: Make sure we test the same inputs on BE as LE. 
With the inexact signed zero support, we ended up with diverging inputs
producing diverging "all skipped" results for the matrix mul tests.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:40 +00:00
Emma Anholt
68f5bc4f12 nir/opt_algebraic_tests: Rename and use the enum result type more. 
As I introduced another layer of iteration for signed zero testing, the
former logic got unwieldy.  In fact, it was already unwieldy enough that I
forgot to clear all_skipped when the assert failed, allowing a failing
test to be marked UNSUPPORTED instead of XFAIL.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:40 +00:00
Emma Anholt
7f1a64e7f5 nir/opt_algebraic_tests: Move more of the base class code to be methods. 
Less passing the *test around separately.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:40 +00:00
Emma Anholt
845e2b3954 nir/opt_algebraic_tests: Remove unnecessary input_count. 
Originally this was for sizing the array, but now we're doing std::vector.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39369>
 2026-01-26 05:39:40 +00:00