Commit graph

93340 commits

Author SHA1 Message Date
Eric Engestrom
cb3e01ca71 mesa/format_info: use designated initialiser list
Also, make that table const, since no-one is supposed to modify it anyway.

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-06-20 17:55:13 +01:00
Eric Anholt
45b0172693 vc4: Clean up release build warnings using MAYBE_UNUSED.
These variables are all used in an assert(), so release builds see no
usages.
2017-06-20 09:09:09 -07:00
Eric Anholt
743dcdd936 vc4: Allow VBOs to be mapped during execution.
There's no reason we can't -- the mappings we expose are basically
equivalent to persistent/coherent, already.

Improves mesa-demos drawoverhead (no state change) performance by
5.21362% +/- 1.25078% (n=11).
2017-06-20 09:05:44 -07:00
Brian Paul
d8148ed10a gallium/vbuf: avoid segfault when we get invalid glDrawRangeElements()
A common user error is to call glDrawRangeElements() with the 'end'
argument being one too large.  If we use the vbuf module to translate
some vertex attributes this error can cause us to read past the end of
the mapped hardware buffer, resulting in a crash.

This patch adjusts the vertex count to avoid that issue.  Typically,
the vertex_count gets decremented by one.

This fixes crashes with the Unigine Tropics and Sanctuary demos with older
VMware hardware versions.  The issue isn't hit with VGPU10 because we
don't hit this fallback.

No piglit changes.

CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-20 08:03:18 -06:00
Brian Paul
2a9d8a45a6 gallium/vbuf: add some const qualifiers
Helps understandability a bit.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-20 08:03:12 -06:00
Brian Paul
ed83e73c4e translate: whitespace fixes in translate_generic.c 2017-06-20 07:56:34 -06:00
Brian Paul
ceb9ca7fa5 softpipe: remove unused softpipe_context::line_stipple_counter
Trivial.
2017-06-20 07:56:34 -06:00
Samuel Pitoiset
ea2492b62f radeonsi: set correct usage flag according to image access type
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-20 13:01:18 +02:00
Marek Olšák
58af1f6bb0 winsys/amdgpu: fix a deadlock when waiting for submission_in_progress
First this happens:

1) amdgpu_cs_flush (lock bo_fence_lock)
   -> amdgpu_add_fence_dependency
   -> os_wait_until_zero (wait for submission_in_progress) - WAITING

2) amdgpu_bo_create
   -> pb_cache_reclaim_buffer (lock pb_cache::mutex)
   -> pb_cache_is_buffer_compat
   -> amdgpu_bo_wait (lock bo_fence_lock) - WAITING

So both bo_fence_lock and pb_cache::mutex are held. amdgpu_bo_create can't
continue. amdgpu_cs_flush is waiting for the CS ioctl to finish the job,
but the CS ioctl is trying to release a buffer:

3) amdgpu_cs_submit_ib (CS thread - job entrypoint)
   -> amdgpu_cs_context_cleanup
   -> pb_reference
   -> pb_destroy
   -> amdgpu_bo_destroy_or_cache
   -> pb_cache_add_buffer (lock pb_cache::mutex) - DEADLOCK

The simple solution is not to wait for submission_in_progress, which we
need in order to create the list of dependencies for the CS ioctl. Instead
of building the list of dependencies as a direct input to the CS ioctl,
build the list of dependencies as a list of fences, and make the final list
of dependencies in the CS thread itself.

Therefore, amdgpu_cs_flush doesn't have to wait and can continue.
Then, amdgpu_bo_create can continue and return. And then amdgpu_cs_submit_ib
can continue.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101294

Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-20 12:53:46 +02:00
Samuel Pitoiset
afeaa2e98a radeonsi: update all resident texture descriptors when needed
To avoid useless DCC fetches when DCC is disabled, descriptors
have to be updated in order to reflect this change. This is
quite similar to how we update descriptors of bound textures.

As a side effect, this should also prevent VM faults when
bindless textures are invalidated, because the VA in the
descriptor has to be updated accordingly as well.

I don't see any performance improvements with DOW3.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-20 10:14:55 +02:00
Samuel Pitoiset
f00e80e3f7 radeonsi: keep track of the sampler state for texture handles
Needed for updating all resident texture descriptors when
dirty_tex_counter changes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-20 10:14:52 +02:00
Lionel Landwerlin
bf5ca4f0b2 i965: perf: use gen_device_info rather then brw_context
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-19 22:11:00 +01:00
Lionel Landwerlin
6d759cbd49 intel: common: add number of thread per eu
This will be used by to normalize OA counters.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-19 22:11:00 +01:00
Lionel Landwerlin
c77d98ef32 intel: common: express timestamps units in frequency
Rather than storing the period as a double that looses some precision.

Also fixes the Gen9LP timestamp frequency which is no 19200123 but
19200000 as pointed by Ville :

https://lists.freedesktop.org/archives/intel-gfx/2017-April/125126.html

Finally add the Cannonlake timestamp frequency.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-19 22:11:00 +01:00
Lionel Landwerlin
e5743ee014 i965: convert MI_REPORT_PERF_COUNT to genxml
Also make it available from gen7 only to gen7+.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-19 22:11:00 +01:00
Lionel Landwerlin
a26f8d99a6 i965: perf: fix codegen with single operand equation
We did support single value operand equations, but not single variable
operand ones. In particular we were failing on "$Sampler0Bottleneck".

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-19 22:11:00 +01:00
Lionel Landwerlin
5f2fe9302c intel: common: add flag to identify platforms by name
The perf infrastructure needs to identify specific platforms, not just
generations.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-19 22:11:00 +01:00
Topi Pohjolainen
b539f6958e i965/wm: Use stored hiz surface instead of creating copy
Now the last user of intel_miptree_get_aux_isl_surf() is gone.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:57:57 +03:00
Topi Pohjolainen
7e4ea22762 i965/blorp: Use hiz surface instead of creating copy
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:57:57 +03:00
Topi Pohjolainen
f60e23cb57 i965/miptree/gen7+: Use isl for hiz layouts
v2: Use better assert by checking isl_surf_get_hiz_surf()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:57:57 +03:00
Topi Pohjolainen
67b44a8423 i965/miptree: Drop BO_ALLOC_FOR_RENDER in intel_miptree_alloc_mcs()
because buffers get unconditionally initialised by cpu writing.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:57:57 +03:00
Topi Pohjolainen
1a43d774b6 i965/miptree: Use isl for mcs layouts
and pass the ccs isl surface to blorp instead of creating a
copy.

v2 (Jason): Explain ccs change and use better assert checking
            isl_surf_get_mcs_surf()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:57:57 +03:00
Topi Pohjolainen
31bd461816 i965/miptree: Refactor aux surface allocation
v2 (Jason): Drop unused argument in intel_alloc_aux_buffer() and
            move assignment of "buf->surf" in intel_alloc_aux_buffer()
            into this patch.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:57:57 +03:00
Topi Pohjolainen
7e25410563 i965/gen6: Use isl for hiz
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:57:57 +03:00
Topi Pohjolainen
59e5519afa i965/miptree: Refactor isl aux usage resolver
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:57:56 +03:00
Topi Pohjolainen
d8a4b8bc88 i965/gen6: Use isl for stencil surfaces
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:57:56 +03:00
Topi Pohjolainen
0e816c9deb i965/miptree: Prepare range getter for isl based
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:57:56 +03:00
Topi Pohjolainen
a808eb172a i965/miptree: Prepare stencil mapping for isl based
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:57:56 +03:00
Topi Pohjolainen
7294cde750 i965/blorp: Prepare for isl based miptrees
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:57:56 +03:00
Topi Pohjolainen
3cf470f2b6 i965: Add isl based miptree creator
v2: Use new brw_bo_alloc_tiled() interface

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:57:44 +03:00
Topi Pohjolainen
5d125f999e i965/miptree: Add option to resolve offsets using isl_surf
v2 (Nanley): Add comment telling why "level -= mt->first_level"

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:41:45 +03:00
Topi Pohjolainen
71ac909137 i965: Prepare slice copy for isl based miptrees
v2 (Jason): Fix a helper variable only used for assert -
            open code instead.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:41:45 +03:00
Topi Pohjolainen
de158c1e43 i965/tex: Prepare image update for isl based miptrees
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:41:45 +03:00
Topi Pohjolainen
bb9c4113dc i965: Prepare framebuffer validator for isl based miptrees
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:41:45 +03:00
Topi Pohjolainen
c05817ffc5 i965: Prepare slice validator for isl based miptrees
v2 (Nanley): Minify depth in case of 3D surface. Also moved to
             .c file to get minify() without additional
             header inclusions

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:41:45 +03:00
Topi Pohjolainen
143e3a679a i965: Prepare image validation for isl based miptrees
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:41:45 +03:00
Topi Pohjolainen
41a7a0e548 i965: Prepare up/downsampling for isl based miptrees
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:41:45 +03:00
Topi Pohjolainen
02fa622037 i965/miptree: Add isl surface
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:41:45 +03:00
Topi Pohjolainen
5a3105fe9a i965: Add helper for converting isl tiling to bufmgr tiling
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:41:45 +03:00
Topi Pohjolainen
a7480d3f03 i965/miptree: Refactor mapping table alloc
v2 (Nanley): Use minify() instead of direct shift

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:41:39 +03:00
Topi Pohjolainen
335543699a i965/gen6: Declare minify(depth, level) layers for 3D stencil
Keeps following patch refactoring the table allocation
non-functional.

Suggested-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:18:53 +03:00
Topi Pohjolainen
a5e1c9f1d5 i965/gen4: Add support for single layer in alignment workaround
On gen < 6 one doesn't have level or layer specifiers available
for render and depth targets. In order to support rendering to
specific level/layer, driver needs to manually offset the surface
to the desired slice.
There are, however, alignment restrictions to respect as well and
in come cases the only option is to use temporary single slice
surface which driver copies after rendering to the full miptree.

Current alignment workaround introduces new texture images which
are added to the parent texture object. Texture validation later
on copies the additional levels back to the surface that contains
the full mipmap.
This only works for non-arrayed surfaces and driver currently
creates new arrayed images in vain - individual layers within the
newly created are still unaligned the same as before.

This patch drops this mechanism and instead attaches single
temporary slice into the render buffer. This gets immediately
copied back to the mipmapped and/or arrayed surface just after
the render is done.

Sitting on top of earlier series cleaning up the depth buffer
state, this patch additionally fixes the following piglit tests:

    arb_framebuffer_object.fbo-generatemipmap-cubemap.g965m64
    arb_texture_cube_map.copyteximage cube.g965m64
    arb_texture_cube_map.copyteximage cube.ilkm64
    arb_pixel_buffer_object.texsubimage array pbo.g965m64
    ext_framebuffer_object.fbo-cubemap.g965m64
    ext_texture_array.copyteximage 1d_array.g45m64
    ext_texture_array.copyteximage 1d_array.g965m64
    ext_texture_array.copyteximage 1d_array.ilkm64
    ext_texture_array.copyteximage 2d_array.g45m64
    ext_texture_array.copyteximage 2d_array.g965m64
    ext_texture_array.copyteximage 2d_array.ilkm64
    ext_texture_array.fbo-array.g965m64
    ext_texture_array.fbo-generatemipmap-array.g965m64
    ext_texture_array.gen-mipmap.g965m64

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:18:53 +03:00
Topi Pohjolainen
a9c59c10a5 i965/miptree: Separate src and dst slice specifiers in slice copy
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:18:53 +03:00
Topi Pohjolainen
920c8e89c5 i965/miptree: Clarify face/level/layer in slice copy
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:18:53 +03:00
Jonas Kulla
a52ee32a9a anv: Fix L3 cache programming on Bay Trail
Valid values for URBAllocation start at 32, so substract that
before programming the register.

This was missed when porting from the GL driver.

Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-19 12:05:52 -07:00
Marek Olšák
3fc99f1299 radeonsi: fix dumping shader descriptors into ddebug logs
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-19 20:16:20 +02:00
Marek Olšák
f9dc29a9a5 radeonsi: add a workaround for inexact SNORM8 blitting again
GFX9 is affected.

We only have tests for GL_x_SNORM where x is R8, RG8, RGB8, and RGBA8.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-19 20:15:36 +02:00
Marek Olšák
0f827b51c0 radeonsi/gfx9: fix TC-compatible stencil compression
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-19 20:15:36 +02:00
Marek Olšák
8a264dd829 radeonsi/gfx9: fix TXF_LZ with 1D textures
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-19 20:15:36 +02:00
Marek Olšák
353b60cab5 radeonsi/gfx9: disable sparse buffers
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-19 20:15:36 +02:00