\[WHY\]
The reason for making these changes is to address the defects identified
by the Coverity scan. By fixing these defects, we can ensure that any
future defects generated by our own code changes can be easily
identified and resolved.
\[HOW\]
To implement the changes/fixes, the following steps were taken:
1. CHECKED_RETURN: All cases were aligned to check the return value.
2. DC.WEAK_CRYPTO: The use of rand() to generate random numbers was
replaced with a more secure method using platofrm API.
3. DEADCODE: Useless code that always returned true was removed.
4. DIVIDE_BY_ZERO: A check was added to ensure that the divisor is not
zero before performing division.
5. HFA: An unused header was removed.
6. MISSING_BREAK: A break statement was added in switch cases where it
was missing.
7. PASS_BY_VALUE: Parameters that were being passed by value and were
too big were changed to pass by reference.
\[TESTING\]
What testings have been done (test IDs and json file):
Reviewed-by: Tomson Chang <Tomson.Chang@amd.com>
Signed-off-by: Min-Hsuan You <Min-Hsuan.You@amd.com>
Acked-by: Chenyu Chen <Chen-Yu.Chen@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32646>
\[WHY\]
System event logs are different than string logging. They are meant to
generate light weight events with ID and variable args and can be
coalesced with events generated by other IP components.
\[HOW\]
Add a callback function, which is implemented by the client (Like PAL)
VPELIB adds defines for a list of possible event IDs
The client is expected to handle the callback
And translate and emit the event through
native system infrastructure like ETW logging.
\[TESTING\]
Tested on system that triggers sys event, and viewed the event through
ETW viewer
Signed-off-by : Anthony Koo <anthony.koo@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chenyu Chen <Chen-Yu.Chen@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32646>
\[WHY\]
Some header files in VPE lib did not have the proper copyright header
\[HOW\]
Proper copyrights were put in place
Reviewed-by: Roy Chan <roy.chan@amd.com>
Co-authored-by: Tiberiu Visan <tvisan@amd.com>
Acked-by: Chenyu Chen <Chen-Yu.Chen@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32646>
Refactor bg gen as it check_bg_support simply calls into other version specific function.
Move that function directly into check_bg_support call, and refactor unnecessary functions + format fix.
Co-authored-by: Brendan <breleder@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Reviewed-by: Navid Assadian <Navid.Assadian@amd.com>
Acked-by: Chenyu Chen <Chen-Yu.Chen@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32646>
ACO is still not perfect:
* It generates s_wait_loadcnt 0x0-0x3 when the only required wait instruction
is s_wait_loadcnt 0x5.
* It generates a lot of unnecessary jumps and blocks for uniform loop breaks.
Only scc1 jumps are necessary to break the loop. This is 10x better than
LLVM, but even ACO might consider using nir_intrinsic_ordered_add_loop_gfx12_amd
for the best performance.
How to print the streamout asm on any GPU:
PIGLIT_PLATFORM=gbm AMD_FORCE_FAMILY=gfx12_16pipe AMD_DEBUG=vs,mono,asm,useaco ../piglit/bin/shader-io-rate vs_out_xfb
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32570>
It's allowed to place OpExecuteCallableKHR in a SPIR-V, even if the RT
pipeline doesn't contain any callable shaders. Unreal hits this case and
crashes. We can assume the intrinsic never gets executed, so we can
simply remove it.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32613>
This is beneficial to applications that rely on
the implicit primitive ID from VS.
- We don't have to disable provoking vertex reuse,
which results in more efficient vertex processing.
- There is no LDS access needed to export the primitive ID,
because it is already available to GS threads.
- As a consequence of not needing LDS, we can use this
together with NGG passthrough mode.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32270>
We want to make the implicit VS primitive ID a per-primitive
output attribute, which means that this has to be last.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32270>
This configuration will be enabled in RADV in a subsequent commit.
On GFX10.3:
Do this together with the primitive export, to avoid adding extra
CF, and to ensure optimal access of the export space.
On GFX11:
It's not an export but a memory store instruction, so always do
it earlier and ensure the optimal attribute ring access pattern.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32270>
It doesn't do anything useful for other stages.
In VS, we use this when the implicit primitive ID is needed,
so that we can export that as a per-vertex attribute of the
provoking vertex.
In TES, the patch ID (which is used as the primitive ID) is
already a per-vertex input VGPR, so it doesn't make sense to
configure this.
In GS, the primitive ID is explicitly written by the shader,
so it makes no sense to disable provoking vertex reuse in the
input.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32270>
Match AMDVLK and radeonsi.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32577>
Match the limit of radeonsi and RADV.
No fossil-db changes.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32577>
This injects a MRTZ export with only the alpha channel to select it
with COVERAGE_TO_MASK_ENABLE for alpha-to-coverage.
Co-Authored-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32583>
Displayable DCC should also be disabled, otherwise it's asserting
somewhere in ac_surface.c
Fixes: e3d1f27b31 ("radv: add radv_disable_dcc_stores and enable for Indiana Jones: The Great Circle")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32584>
ttmp sgprs are readonly outside of trap handlers, so the instructions were
probably skipped. RA should also never create additional exec writes.
Fixes: e06773281b ("aco/ra: Optimize some SOP2 instructions with literal to SOPK.")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32545>
On AMD hardware, it's possible to export a separate alpha channel for
applying alpha-to-one after alpha-to-coverage and not before.
On GFX11+, it's already mostly supported but alpha needs to be exported
to MRTZ.a and one to MRT0.a. The hw always uses alpha for
alpha-to-coverage from MRTZ.a.
On older generations, the driver needs the same separate alpha export
but it also needs to configure the hardware with COVERAGE_TO_MASK_ENABLE
which selects alpha from MRTZ.a.
This should fix alpha-to-coverage with alpha-to-one when either
depth, stencil or samplemask are exported but it still needs a slightly
different solution without MRTZ. I will fix that later.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32523>
When alpha-to-coverage and alpha-to-one are both enabled in the
fragment shader, the alpha value should be exported through MRTZ and
one to MRT0.a. Otherwise, alpha-to-one will be performed before
alpha-to-coverage.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32523>
It's just completely broken if alpha-to-coverage is also used. Given
this is a requirement for Zink and no known GL apps are affected, let's
disable for everything except Zink. This is going to be fixed but the
fixes aren't small enough for backporting.
This fixes a rendering issue with XPlane 12.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32576>
Right now the driver doesn't support multi-slice encodes, so
report the correct value.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Autumn Ashton
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32580>
