We will get shader_info from NIR after this and before si_init_shader_args,
so we need to use system values.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
We don't need to look at the framebuffer state and record how many color
buffers to write. Instead, we can deduce which color buffers are enabled
from spi_shader_col_format, which already does the right thing.
So PS epilogs only need a single bool flag that determines whether all
enabled color buffers should be written.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
This adds an option into the prolog key to replace frag_coord.xy with
pixel_coord when sample shading is disabled, which is most of the time.
This reduces the number of input VGPRs.
It's already implement in ac_nir_lower_ps_early for monolithic shaders
and the PS prolog in ACO, so this just implements it for the PS prolog
in LLVM IR.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
Using the used component count is not enough. We need to consider
the component mask because any component can be disabled. This might
fix tests.
This removes the component counting from ac_get_fs_input_vgpr_cnt
and determines the component mask where it's needed.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
This should be faster.
2 user SGPRs contain 8 sample positions, storing 4 bits per coordinate
and extracting them in the shader.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
Liveness info can be huge, since with larger shaders it essentially
grows quadratically (linear increase in number of SSA defs *
linear increase in blocks).
Freeing liveness info early helps somewhat mitigate memory usage here.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29577>
The checksum for the Osmos trace on TGL has changed, so update it
to reflect the current state of the trace.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Reviewed-by: Mike Blumenkrantz <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33256>
This trace contains generated GL IDs from the time it was recorded,
making it invalid.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Reviewed-by: Mike Blumenkrantz <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33256>
LLVM 15 is pretty old, and notably not supported by either ANGLE nor
Skia anymore. So let's move up to LLVM 19 using packages provided by
LLVM themselves, apart from PPC and ARMv7 which don't have builds.
The Skia build now requires a bunch of new warning exclusions; hopefully
most of these are no longer needed when we can upgrade Skia shortly.
The ci-deb-repo revision has also been bumped to get us a new version of
xtensor which builds with LLVM 19, and a version of spirv-tools which
also works with LLVM 19.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Closes: mesa/mesa#11538
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33137>
When building for the dynamic loader used by e.g. Clover, pipe_i915 was
the only target failing to declare a driver descriptor. This becomes an
error with more aggressive linkers.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Fixes: 87392385b5 ("gallium/drm: Define the DRM entrypoints in drm_helper.h")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33137>
NEW util/conversion.rs
Adds traits `TryFromWithErr` and `TryIntoWithErr` and their
implementation for types with `TryFrom` and `TryInto` traits
former
```
try_into().map_err(|_| CL_OUT_OF_HOST_MEMORY)
try_from(val).map_err(|_| CL_OUT_OF_HOST_MEMORY)
```
can now be written as
```
try_into_with_err(CL_OUT_OF_HOST_MEMORY)
try_from_with_err(val, CL_OUT_OF_HOST_MEMORY)
```
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33267>
cat3 instructions read their 3rd src later than their first two srcs.
Pre-a7xx, this was only supported for mad(sh) but on a7xx, it works for
all cat3 instructions.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33183>
cat3 instructions read their 3rd src later than their first two srcs.
This was implemented in two different places: once for scheduling and
once for legalization. Extract this logic in a new helper and also add
similar logic for gat/swz there (which the scheduling logic failed to
account for).
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33183>
Preamble defs were rematerialized at the end of the preamble. However,
when some of the sources were defined inside control flow, this would
lead to these sources not dominating their use. Fix this by finding the
block that is dominated by all sources and inserting the new instruction
there.
Also make sure we only de-duplicate instructions if the new instruction
is dominated by the existing one.
Fixes a NIR validation error in Devil may cry 5.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: fdfe86aa52 ("ir3: Expand preamble rematerialization")
Fixes: 6a744ddebc ("ir3: Initial support for pushing globals with ldg.k")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33270>
This was accidentally deleted when rewriting to use common Vulkan
dynamic state. This meant we wouldn't correctly fall back when someone
accidentally used FDM together with multiple viewports.
Fixes: 97da0a7734 ("tu: Rewrite to use common Vulkan dynamic state")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33241>
Scheduling an alias.rt right before an alias.tex causes a GPU hang.
Follow the blob and schedule all alias.rt at the end of the preamble to
prevent this from happening.
Fixes a hang in Borderlands 3 on medium or higher graphics settings.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 0aa9678d4d ("ir3: add support for alias.rt")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33238>
just accept the arguments as-is. this matches how gcc/clang actually work
and simplifies the meson.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33242>
reduces a bit of boilerplate.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33242>
center mv map buffer size changed on vcn5.x, please be aware
that vcn5.0 will not enable 2pass untill vcn5.x.
Reviewed-by: David Rosca <david.rosca@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33215>
Xe KMD originally put the exec queue snapshot in the wrong topic,
XE_TOPIC_GUC_CT. Add it to the right one while still keeping a fallback
to the previous place so the new version of the tool is able to parse
both before and after the kernel change.
Based on previous version by José Roberto de Souza <jose.souza@intel.com>
at https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32617
Cc: stable
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33177>
Textures opcodes can't read from the contant registers, however we can
just handle this fine in the native swizzle pass. Others like saturate
for tex instructions) can't happen anyway since we swithed to nir_to_tgsi
long time ago. However, keep the asserts just to be safe.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
The pass tried to convert shaders to a SSA-like form. However since
we no longer allocate registers in NIR, and we try hard to keep the
SSA-like form during the later passes, this is now superfluous.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
So we can get the ssa-like form right away and we don't have to generate
it again with the register rename pass later.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
Lots of backend code will be simpler if we have ssa-like (as much as we
can have with vec4), so just don't reuse registers here.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
Prevents shader-db regression, since NIR puts just everything to x and the
pair scheduling is not smart enough to fix it later, espetially after
presubtract happens.
Together with the previous patches that move the shadow lovering to NIR
this results in the following shader-db stats:
RV530:
total instructions in shared programs: 129598 -> 128697 (-0.70%)
instructions in affected programs: 19001 -> 18100 (-4.74%)
helped: 124
HURT: 9
total presub in shared programs: 8554 -> 8314 (-2.81%)
presub in affected programs: 1099 -> 859 (-21.84%)
helped: 17
HURT: 50
total temps in shared programs: 17514 -> 17000 (-2.93%)
temps in affected programs: 1368 -> 854 (-37.57%)
helped: 45
HURT: 18
total cycles in shared programs: 191286 -> 190593 (-0.36%)
cycles in affected programs: 32369 -> 31676 (-2.14%)
helped: 110
HURT: 29
RV410:
total instructions in shared programs: 112805 -> 112618 (-0.17%)
instructions in affected programs: 7089 -> 6902 (-2.64%)
helped: 65
HURT: 21
total presub in shared programs: 3244 -> 3314 (2.16%)
presub in affected programs: 228 -> 298 (30.70%)
helped: 7
HURT: 47
total temps in shared programs: 18163 -> 18138 (-0.14%)
temps in affected programs: 710 -> 685 (-3.52%)
helped: 36
HURT: 19
total cycles in shared programs: 169530 -> 169369 (-0.09%)
cycles in affected programs: 11304 -> 11143 (-1.42%)
helped: 63
HURT: 27
The stats are a bit less awesome for Rv410, since it can't run the heavy
Unigine Tropics shaders where this helps the most due to the TEX
indirection limits.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
This means we now do fragment shader-variants at the NIR level and we
therefore need to run nir_to_rc translation later during the shader
variant creation.
This is a temporary instruction count as well as registers count
regression, due to NIR putting everything to x instead of w, this is
fixed in the next commit which also shows some nice shader-db stats
improvements in total.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
We only care that the negates of the relevant components are the same.
Specifically the assert would incorectly trigger for code like this
ADD temp[3].x, 1.250000 (0x3a).-x___, -const[0].x___;
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
