Commit graph

14970 commits

Author SHA1 Message Date
Francisco Jerez
a48ecca4d9 intel/brw/gfx12.0+: Sync on all pending send messages after halt target.
This works around a long-standing synchronization issue consequence of
the HALT instruction used to implement FS discard not being considered
a control flow instruction by the back-end -- The fact that it doesn't
cause the CFG pass to introduce an edge in the graph means that the
software scoreboard pass is completely blind to the effect of discard
jumps on control flow, so it doesn't introduce the required
annotations to avoid data hazards when the discard path of the CFG is
taken.  Note that because of the very limited set of instructions that
can follow the HALT target in a fragment shader this was very unlikely
to lead to issues in practice, but starting on xe3 it appears to have
become far more likely due to the use of SENDG, since SENDG requires
the scalar register to be set prior to the submission of the render
target write payloads, which can easily lead to a WaR hazard if there
was another SENDG before the HALT jump that wasn't done reading out
its payload from the GRF.

In an ideal world this would be avoided by having HALT be a normal
control flow instruction represented as an edge in the control flow
graph -- But unfortunately that would prevent the optimizations we
currently do that take advantage of the ability of reordering code
past the HALT instruction, so it would have a pretty large performance
cost.  Instead this simply adds a SYNC.ALLWR instruction after the
HALT target to guarantee that all pending SEND messages have finished
execution -- That may also seem costly, however its cost in practice
appears to be minimal since at the point of the program when the
target HALT is executed there is almost nothing left to do other than
send out the render target write payloads, so any pending operations
had to be waited on at roughly this point of the program regardless.

There appear to be no statistically significant regressions in Traci
on neither BMG nor PTL.  Fixes hangs observed on Dying Light 2 and
Cyberpunk on PTL.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13896
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13965
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14092
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37674>
2025-10-15 01:40:22 +00:00
Lionel Landwerlin
988d3dbc39 intel/ci: remove old comments
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Should have been removed with the CTS uprev.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37877>
2025-10-15 01:10:49 +00:00
José Roberto de Souza
ce25f12975 intel/brw: Add comment to first_non_payload_grf
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37853>
2025-10-14 18:26:39 +00:00
José Roberto de Souza
6e02351c58 intel/brw: Share mode code in lower_lsc_varying_pull_constant_logical_send()
By dynamic setting num_channel we can share more code in
lower_lsc_varying_pull_constant_logical_send().

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37853>
2025-10-14 18:26:39 +00:00
Sagar Ghuge
77d2197c18 Revert "intel: Always set Cube Face Enables for all surfaces."
This reverts commit bf15dc7a1b.

All credit goes to Lionel, he spotted this difference. How much effort
went in for this god knows.

Closes: #12348 #12816 #12446 #12387 #12827 Related #12847 #12520
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37498>
2025-10-13 11:54:11 -07:00
Hyunjun Ko
ecfbcd3d7d anv/ci: added video tests failures on tgl/jsl
Since we don't support filmGrainSupport on previous of gen20 for AV1
decoding by default, failures start happening due to the video tests
assuming always FG supported, which is a fault of CTS.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37762>
2025-10-13 12:06:24 +00:00
Hyunjun Ko
cf04badfb4 anv/video: remove support for VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT
Since we always return (DPB | DST) for video image usages, (See the
discussion at https://gitlab.khronos.org/vulkan/vulkan/-/issues/4461)
we can't support VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT, which was
disabled for DST usages.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37762>
2025-10-13 12:06:24 +00:00
Hyunjun Ko
29aacd7904 anv/video: Make the query result for video profiles and formats more
precisely.

This way we could provide more correct infomation to applications.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37762>
2025-10-13 12:06:24 +00:00
Caio Oliveira
74859c19fb intel/executor: Add a matrix multiplication example
Some checks are pending
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Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37805>
2025-10-11 01:02:45 +00:00
Caio Oliveira
1e0ee84841 intel/executor: Add DPAS examples for HF/F, UB/UD and BF/F
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37805>
2025-10-11 01:02:45 +00:00
Caio Oliveira
62f07dc5e3 intel/executor: Add script directory to package.path
In Lua, modules (i.e. files with lua code) are loaded by using
the standard library require(), e.g.

```
local mylib = require("mylib")

mylib.do_something()
```

The require() will decide where to look by peeking at `package.path`
table.  By default it doesn't include the scripts directory, so running
executor from the script directory vs. from the root of the repo would
yield different results (require works vs. require fail to find the
module).  This patch includes the script directory to avoid this issue.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37805>
2025-10-11 01:02:45 +00:00
Caio Oliveira
86947062e9 intel/executor: Expose a devinfo table
So we can pull other values from devinfo struct.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37805>
2025-10-11 01:02:44 +00:00
Caio Oliveira
5987269750 intel/executor: Drop check_ver and check_verx10 functions
Favor explicit version checks, that can use different types of
comparisons other than equality on a list.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37805>
2025-10-11 01:02:44 +00:00
Lionel Landwerlin
febac6d9bd anv: fix query copy with shaders
Some checks are pending
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First this is only possible on RCS or CCS engines.

Second if on CCS, we need to use a compute shader, 3D won't work.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37818>
2025-10-10 21:31:09 +00:00
Ian Romanick
ca493b5c45 brw: elk: Fix name of function in comment
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Trivial.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37186>
2025-10-10 17:25:11 +00:00
Ian Romanick
b948e6d503 brw: Use BFN to implement nir_opt_bitfield_select
shader-db:

Lunar Lake, Meteor Lake, and DG2 had similar results. (Lunar Lake shown)
total instructions in shared programs: 17181559 -> 17181254 (<.01%)
instructions in affected programs: 250921 -> 250616 (-0.12%)
helped: 303 / HURT: 0

total cycles in shared programs: 888542568 -> 888543370 (<.01%)
cycles in affected programs: 49861772 -> 49862574 (<.01%)
helped: 181 / HURT: 110

fossil-db:

Lunar Lake, Meteor Lake, and DG2 had similar results. (Lunar Lake shown)
Totals:
Instrs: 233260591 -> 233260196 (-0.00%); split: -0.00%, +0.00%
Cycle count: 32754501248 -> 32754567116 (+0.00%); split: -0.00%, +0.00%
Max live registers: 71738476 -> 71738442 (-0.00%)
Non SSA regs after NIR: 67837262 -> 67837108 (-0.00%); split: -0.00%, +0.00%

Totals from 226 (0.03% of 790721) affected shaders:
Instrs: 382227 -> 381832 (-0.10%); split: -0.15%, +0.05%
Cycle count: 72863878 -> 72929746 (+0.09%); split: -0.65%, +0.74%
Max live registers: 36557 -> 36523 (-0.09%)
Non SSA regs after NIR: 60427 -> 60273 (-0.25%); split: -0.26%, +0.00%

No shader-db or fossil-db changes on any previous Intel platforms.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37186>
2025-10-10 17:25:11 +00:00
Ian Romanick
4193895145 brw/cmod: Enable limited cmod propagation for BFN
cmod propagation needs more work. Since the result type is always UD,
BRW_CONDITION_G should be able to substitute for NZ. Either that or
users of the condition could be rewritten to use an inverted condition.

v2: Add a couple more unit tests. Suggested by Matt.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37186>
2025-10-10 17:25:11 +00:00
Ian Romanick
fb193ac190 brw/builder: Add BFN
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37186>
2025-10-10 17:25:10 +00:00
Ian Romanick
a947e0c4db brw: Constant propagation and constant combining support for BFN
v2: Commute immediate values out of src[1].

Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37186>
2025-10-10 17:25:10 +00:00
Ian Romanick
8a71f5e672 brw: BFN does not support source modifiers
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37186>
2025-10-10 17:25:10 +00:00
Ian Romanick
60c07e500d brw: Basic validation for BFN
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37186>
2025-10-10 17:25:10 +00:00
Ian Romanick
d2077e24f6 brw/disasm: Pretty print the BFN equation as an annotation
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37186>
2025-10-10 17:25:09 +00:00
Ian Romanick
fdb01f2a5a brw/disasm: Fix BFN disassembly of src1 and src2
The negate and abs bits of src1 and src2 are repurposed for some of the
function control value bits.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37186>
2025-10-10 17:25:09 +00:00
Zach Battleman
ca2a067469 brw: Initial bits of BFN support
v2 (idr): So much rebasing. Deleted a bunch of code that we're not
going to need yet.

v3 (Ken): bfn inst encoding fix

v4 (idr): Add BFN to brw_get_lowered_simd_width.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37186>
2025-10-10 17:25:09 +00:00
Ian Romanick
073ffceef6 elk: Enable saturating float to integer conversion opcodes
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37186>
2025-10-10 17:25:06 +00:00
Ian Romanick
65e8220180 brw: Enable saturating float to integer conversion opcodes
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37186>
2025-10-10 17:25:06 +00:00
Lionel Landwerlin
b8ae4ede60 brw: add serialize send stats
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Alyssa Anne Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37394>
2025-10-10 11:19:39 +00:00
Lionel Landwerlin
37a9c5411f brw: serialize messages on Gfx12.x if required
The Intel EU fusion feature needs to be disabled on SEND messages
where either the texture handle, sampler handle, sampler header is not
identical on fused threads.

This is the case in particular with accesses on non-uniform
texture/sampler handles but could also strike with dynamic
programmable offsets (currently disabled).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Anne Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37394>
2025-10-10 11:19:39 +00:00
Kenneth Graunke
dd9e002129 brw: Fix mesh shader asserts in clip/cull distance setting
mesh doesn't use brw_vue_prog_data.  Also, I had been catching TCS
shaders here, and shouldn't.

Fixes: bf76e86bc8 ("brw: Refactor clip/cull distance mask setting into a helper")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37809>
2025-10-10 09:51:26 +00:00
Lionel Landwerlin
196c7903b9 anv: fix companion usage for emulated image
Some checks are pending
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We need to return true if we need the companion batch.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e60416b4e4 ("anv: use companion batch for operations with HIZ/STC_CCS destination")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37797>
2025-10-09 21:38:33 +00:00
Kenneth Graunke
bb096b0f12 brw: Use BITFIELD_{MASK,RANGE} in clip/cull distance mask handling code
Suggested by Alyssa.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37784>
2025-10-09 13:20:04 -07:00
Kenneth Graunke
bf76e86bc8 brw: Refactor clip/cull distance mask setting into a helper
This was copy pasted between 4 different stages.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37784>
2025-10-09 13:20:03 -07:00
Kenneth Graunke
b3c511592a brw: Replace type_size_xvec4 with glsl_count_attribute_slots
This is nearly identical, except for bindless sampler/texture/image
handling.  But we only use it for inputs/outputs, not uniforms, where
there are no bindless handles to worry about.

Deletes a lot of mostly-duplicated code.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37784>
2025-10-09 13:20:00 -07:00
Kenneth Graunke
a12f117cef brw: Stop using type_size_dvec4 for fragment shader outputs
There are no 64-bit renderable formats so we can't have FS outputs that
are dvecs.  This dates back to 2016 and a ton of the backend has been
rewritten, so I think whatever this was trying to solve is no longer a
problem.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37784>
2025-10-09 13:19:56 -07:00
Lucas Fryzek
3a124ac82a anv: Enable VK_ANDROID_external_format_resolve
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37177>
2025-10-09 18:42:13 +00:00
Lucas Fryzek
eb70d66228 anv: Add external format resolve operation using blorp
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37177>
2025-10-09 18:42:13 +00:00
Lucas Fryzek
bbcafa630f anv: Modify anv feature (dis)enable code to match other drivers
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37177>
2025-10-09 18:42:13 +00:00
Lucas Fryzek
1b333251c4 anv: Enable R10X6 & R10X6G10X6 unorm formats
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37177>
2025-10-09 18:42:13 +00:00
Lucas Fryzek
232f8c42f7 anv: Assert that we only import ahb image with one layer
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37177>
2025-10-09 18:42:13 +00:00
Alyssa Rosenzweig
ee671cf4f7 intel/nir_blockify_uniform_loads: use helpers
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37753>
2025-10-09 09:50:20 -04:00
Alyssa Rosenzweig
6b006db492 brw/nir_lower_storage_image: use helper
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37753>
2025-10-09 09:50:20 -04:00
Alyssa Rosenzweig
e3b6440b39 brw/nir_lower_shader_calls: use helpers
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37753>
2025-10-09 09:50:20 -04:00
Alyssa Rosenzweig
ec8ed69131 brw/nir_lower_sample_index_in_coord: use helpers
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37753>
2025-10-09 09:50:20 -04:00
Alyssa Rosenzweig
544a739abc brw/nir_lower_fs_barycentrics: avoid nir_def_rewrite_uses_after
replace is preferred when appropriate & should be faster. after is when
you use the result in your lowering itself.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37753>
2025-10-09 09:50:19 -04:00
Alyssa Rosenzweig
4fe8c19862 brw/nir_lower_alpha_to_coverage: eliminate goto
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37753>
2025-10-09 09:50:19 -04:00
Kenneth Graunke
73cbb35442 brw: Move into a new src/intel/compiler/brw subdirectory
Some checks are pending
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This keeps the directory structure a bit more organized:
- brw specific code
- elk specific code
- common NIR passes that could be used in both places

It also means that you can now 'git grep' in the brw directory without
finding a bunch of elk code, or having to "grep thing b*".

Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37755>
2025-10-09 07:01:47 +00:00
Kenneth Graunke
d1b0597213 brw: Drop compiler/ from brw includes
They're in the current directory/module, just include them.

Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37755>
2025-10-09 07:01:46 +00:00
Kenneth Graunke
af93215b7a intel: Re-unify brw_prim.h and elk_prim.h
These are identical and are just hardware enum values, not related to
the structure of the backend compiler.

Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37755>
2025-10-09 07:01:46 +00:00
Kenneth Graunke
d4c8ca43ef intel: Make a libintel_compiler_nir internal static library
We were compiling these twice, one for brw, one for elk.  There's no
reason to do that, just compile the common code once and link against it
in both backends.

Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37755>
2025-10-09 07:01:46 +00:00
Kenneth Graunke
86aa241c66 brw: Rename brw_nir_trig build target to brw_nir_workarounds
Matches the recent file rename.

Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37755>
2025-10-09 07:01:46 +00:00