We haven't wired this up in the Midgard compiler, so we can't expose
sample shading on Midgard GPUs. This all seems fixable, because the KILL
instruction can update the coverage without the kill-flag (yeah, a bit
confusing naming), but until someone puts in the time to wire up that,
let's just disable the functionality to avoid crashes.
Fixes: 6bba718027 ("panfrost: Advertise SAMPLE_SHADING")
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35881>
Previously we had to utilize the 3D path for float16 formats since
the hw would implicitly convert f16->f32 canonicalizing NaNs
resulting in copies that were not bit exact.
The `HALF_PRECISION` bit was discovered which avoids this
conversion, so we can go back to using the 2D path.
Using the 2D path is faster than the 3D path. Results of Crucible
bench.cast-image show an improvement of slightly above a 50% average
for the 1 MiB image->image copy of {4,6,16,32,64)B chunks, and for
the 16 GiB there's a slight improvement.
The affected formats are {R16,R16G16,R16G16A16}_SFLOAT.
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35709>
We're now re-emitting push constants at the
start of compute batches, so we can avoid the
overhead of restoring them.
CC: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35873>
Per Ken Graunke, corruption issues with push
constants for render batches on Gen12 graphics
have been observed and worked around by re-emitting
push constants at the start of the batch buffer.
We're seeing similar issues with compute batches,
so we'll apply the same work-around.
Fixes corruption reported in Blender on ADL/RPL
CC: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35873>
We're currently not using image layouts in PanVK so we can advertise
this extension without additional changes.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: John Anthony <john.anthony@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35911>
We have enough DUTs to increase the job parallelism to 8. At this level,
the runtime reported by deqp-runner averages about 8:30, which is below
the 10-minute target recommended by the docs.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35913>
The sm8350-hdk has 8 threads and 12 GB of RAM, which allows increasing
`FDO_CI_CONCURRENT` to 9 to speed up the job.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35906>
Following the previous commit, we have an additional `parallel:` slot
available.
Use it to run `a660-gl-cl` without a fraction, allowing us to remove the
nightly `a660-gl-full` job.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35906>
The actual runtime of `a660-piglit-cl` is under 2 minutes, so it can be
merged into `a660-gl` to improve resource utilization by avoiding the
launch of the additional job.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35906>
The actual runtime of `a618-piglit-cl` was under 2 minutes, so it can be
folded into the main `a618-piglit` job.
To accommodate this, the "gpu" profile's fraction was fully moved to the
deqp-runner suite without changing the overall test coverage:
`fraction = 3` * `DEQP_FRACTION: 2` = 6
Also drop the redundant freedreno-a618-skips.txt skip while we're here,
as that's automatically picked up via GPU_VERSION.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35906>
Aliased wsi image has to share the same private binding with the
original wsi image for memory consistency. If the private binding
exists, it needs to be released before being overridden.
Fixes: d85a9d658f ("anv/image: Call into WSI to create swapchain images")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35893>
The JOB_OFFSET only actually affect the global id and not wg id.
In NIR common, we assume that if base wg isn't supported, it means that
global and wg id already contains it.
To follow the convention around, we remove the offset to assume
global id will need an offset added.
Alone, this doesn't change functionality as we always lower away global
id so far.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35909>
make sure we can fold the f2f away. alternatively f2fmp would work
here but details.
elden ring:
Totals from 137 (4.27% of 3206) affected shaders:
Instrs: 485455 -> 484904 (-0.11%)
CodeSize: 3218638 -> 3215338 (-0.10%)
ALU: 308071 -> 307520 (-0.18%)
FSCIB: 308071 -> 307520 (-0.18%)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35909>
for drivers where we need to lower a base_workgroup_id but not global IDs.
rather than lowering the whole global ID to stick the base workgroup ID in
there, just add the workgroup offset to the final thread position.
Elden ring fossils:
Totals from 52 (1.62% of 3206) affected shaders:
Instrs: 48355 -> 48233 (-0.25%); split: -0.31%, +0.06%
CodeSize: 331912 -> 331148 (-0.23%); split: -0.28%, +0.05%
ALU: 30853 -> 30674 (-0.58%); split: -0.70%, +0.12%
FSCIB: 30853 -> 30674 (-0.58%); split: -0.70%, +0.12%
IC: 9054 -> 8958 (-1.06%)
GPRs: 4184 -> 4216 (+0.76%)
Uniforms: 6703 -> 6677 (-0.39%); split: -1.61%, +1.22%
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35909>
The Midgard compiler only deals with sized NIR types for image loads and
stores. Since we already have nir_get_nir_type_for_glsl_base_type()
which can provide us with the corresponding sized type, let's just use
that, and drop the extra table.
This fixes the following piglits on Mali-T760:
- spec/ext_texture_compression_s3tc/getteximage-targets 2d s3tc
- spec/ext_texture_compression_s3tc/getteximage-targets cube s3tc
Fixes: 9123ee0f18 ("st/mesa/pbo: Set src type on image_store")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35882>
For emulated multiplanar formats like PIPE_FORMAT_IYUV /
DRM_FORMAT_YUV420 resource->format is set to one of the sub-
formats, PIPE_FORMAT_R8_UNORM in this case. As this has only
one plane, users like `dri2_from_planar()` fail for queries
where plane > 0. This in turn breaks queries like
gbm_dri_bo_get_handle_for_plane() which is commonly used
by Wayland compositors to offload client supplied DMABufs
to KMS, using drmModeAddFB2WithModifiers().
Follow the example of most other drivers and return the number
of resources instead.
Signed-off-by: Robert Mader <robert.mader@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35915>
os_mkdir() is a simple wrapper around mkdir() or _mkdir().
Remove a bunch of unneeded #includes in dd_util.h. Testing by
compiling llvmpipe and radeonsi (the only user of the dd_util.h
header).
There's a few other mkdir() callsites that I haven't touched but
could be updated to os_mkdir().
Signed-off-by: Brian Paul <brian.paul@broadcom.com>
Tested-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35841>
Suse Linux Enterprise 15 is still on g++ 7.5 so std::filesystem
does not exist. Just use mkdir() instead.
Signed-off-by: Brian Paul <brian.paul@broadcom.com>
Tested-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35841>
Wa_16018063123 is not a workaround that depends on stepping, so we
can use the INTEL_WA_16018063123_GFX_VER macro to reduce code generate
for non affected platforms.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35700>
Wa_16018063123 is not a workaround that depends on stepping, so we
can use the INTEL_WA_16018063123_GFX_VER macro to reduce code generate
for non affected platforms.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35700>
Wa_16018063123 don't apply to video engine also video engine don't
support XY_FAST_COLOR_BLT.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Fixes: ec43c20182 ("anv: implement dummy blit for Wa_16018063123")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35700>
For 3D or GPGPU modes the same render engine should be used, CCS
register should only be used when using compute engine.
Fixes: 46f5359238 ("anv: Invalidate aux map for copy/video engine")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35700>
In the following commits, as we split up a6xx.xml, the #include sequence
gets a bit more complicated. Let's keep it in one place.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35899>
This was added on the kernel side in commit 9d78f0250322
("drm/msm/a6xx+: Don't let IB_SIZE overflow"), but didn't
end up in mesa.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35899>
