Commit graph

160248 commits

Author SHA1 Message Date
Yonggang Luo
0c298c1bb2 mapi: Fixes non-constant-expression cannot be narrowed from type 'unsigned long' to 'unsigned int' in initializer list with clang
error is:
../src/mapi/glapi/tests/check_table.cpp:563:19: error: non-constant-expression cannot be narrowed from type 'unsigned long' to 'unsigned int' in initializer list [-Wc++11-narrowing]
   { "glNewList", _O(NewList) },

This is just a test and only with clang, and can be disabled by compiler option, so there is no need to back ported

Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23793>
2023-06-22 11:08:11 +00:00
Yonggang Luo
7af2c45947 mapi: Fixes check_table.cpp for DrawArraysInstancedARB and DrawElementsInstancedARB
The compile error when compiled with "-Dglx=xlib -D shared-glapi=disabled":
check_table.cpp:1133:37: error: ‘struct _glapi_table’ has no member named ‘DrawArraysInstancedARB’; did you mean ‘DrawArraysInstanced’?
 1133 |    { "glDrawArraysInstancedARB", _O(DrawArraysInstancedARB) },

Fixes: 5679ef99b8 ("glapi: remove EXT and ARB suffixes from Draw functions")

Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23793>
2023-06-22 11:08:11 +00:00
Karol Herbst
29b4c1a09f rusticl: experimental support for cl_khr_fp16
Hidden behind `RUSTICL_ENABLE=fp16` for now as the OpenCL CTS doesn't have
enough fp16 tests at the moment. There has been a lot of work on it though,
so hopefully we can enable and verify it soon.

Additionally libclc also misses a bunch of fp16 functionality, so most of
the tests would also just crash.

However this flag is useful for development as it already wires up most of
the code needed.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Nora Allen <blackcatgames@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23788>
2023-06-22 10:45:48 +00:00
Karol Herbst
6ae801c4d8 rusticl/device: rename doubles to fp64 and long to int64
They are obviously the better names.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Nora Allen <blackcatgames@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23788>
2023-06-22 10:45:48 +00:00
David Heidelberg
0623e1784c ci/panfrost: switch panfrost-g52-piglit-gles2 from X to XWayland
Runtime reduced approx. by 3 minutes (~ 11 to 8 minutes).

 - Add spec@ext_image_dma_buf_import@ext_image_dma_buf_import-transcode-nv12-as-r8-gr88 crash
 - drop useless `.piglit-test` extend

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23785>
2023-06-22 10:27:38 +00:00
norablackcat
5c120173b3 zink/screen: add PIPE_CAP_TIMER_RESOLUTION
Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>
2023-06-22 09:08:33 +00:00
norablackcat
79cd51d0e6 radeonsi/get: add PIPE_CAP_TIMER_RESOLUTION
Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>
2023-06-22 09:08:33 +00:00
norablackcat
979f47a04d r600/pipe: add PIPE_CAP_TIMER_RESOLUTION
Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>
2023-06-22 09:08:33 +00:00
norablackcat
6e1f873a0c iris/screen: add PIPE_CAP_TIMER_RESOLUTION
Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>
2023-06-22 09:08:33 +00:00
norablackcat
d27040ed89 crocus/screen: add PIPE_CAP_TIMER_RESOLUTION
Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>
2023-06-22 09:08:33 +00:00
norablackcat
6ec57403db sofpipe/screen: add PIPE_CAP_TIMER_RESOLUTION
Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>
2023-06-22 09:08:33 +00:00
norablackcat
35f5bc0ad4 llvmpipe/screen: add PIPE_CAP_TIMER_RESOLUTION
Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>
2023-06-22 09:08:33 +00:00
norablackcat
660f2eabe1 gallium: add PIPE_CAP_TIMER_RESOLUTION
Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>
2023-06-22 09:08:33 +00:00
Marek Olšák
77f5b1cce0 radeonsi: clean up #includes
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
2023-06-22 08:35:55 +00:00
Marek Olšák
56c787b36d radeonsi: declare compiler[] and nir_options as pointers to reduce #includes
so that we don't have to include the structure definitions.
(ac_llvm_compiler includes LLVM, and nir_options includes NIR)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
2023-06-22 08:35:55 +00:00
Marek Olšák
620ff256a2 radeonsi: clean up query functions, make them static, remove forward decls
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
2023-06-22 08:35:55 +00:00
Marek Olšák
69bc1180b7 radeonsi/gfx11: use SET_SH_REG_PAIRS_PACKED for compute by buffering reg writes
This is the compute portion of the work. It uses a separate buffer
for compute SH registers in si_context.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
2023-06-22 08:35:55 +00:00
Marek Olšák
1753b321f8 radeonsi/gfx11: use SET_SH_REG_PAIRS_PACKED for gfx by buffering reg writes
Instead of writing SH registers into the command buffer, push them into
an array in si_context. Before a draw, take all buffered register writes
and create a single SET_SH_REG_PAIRS_PACKED packet for them.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
2023-06-22 08:35:55 +00:00
Marek Olšák
a6e6646d91 radeonsi: reorder compute code to prepare for packed SET_SH_REG packets
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
2023-06-22 08:35:55 +00:00
Marek Olšák
f71607c8d3 radeonsi/gfx11: enable register shadowing by default
required by SET_SH_REG_PAIRS_PACKED*

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
2023-06-22 08:35:55 +00:00
Marek Olšák
aafef61f6a radeonsi/gfx11: fix GLCTS with register shadowing by keeping the CS preamble
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
2023-06-22 08:35:55 +00:00
Marek Olšák
c7f4ffa401 radeonsi: remove uses_reg_shadowing parameter from si_init_gfx_preamble_state
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
2023-06-22 08:35:55 +00:00
Marek Olšák
913c6392f6 radeonsi: remove radeon_winsys::cs_set_preamble
It only does radeon_emit_array and it's not possible to do anything better.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
2023-06-22 08:35:55 +00:00
Marek Olšák
c4811edfa6 radeonsi: use si_pm4_create_sized for the shadowing preamble
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
2023-06-22 08:35:55 +00:00
Marek Olšák
fff585bdb8 radeonsi: don't do BREAK_BATCH for context regs with only 1 context per batch
because it has no effect

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
2023-06-22 08:35:55 +00:00
Marek Olšák
835190dd9f radeonsi: keep pipeline statistics disabled when they are not used
so that we don't always disable/enable pipeline stats around blits
when there are no pipeline stat queries

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
2023-06-22 08:35:54 +00:00
Marek Olšák
ccb856fbaa radeonsi: determine si_pm4_state::reg_va_low_idx automatically
The existing code doesn't work with the packed SET packets, so si_pm4_state
needs to find reg_va_low_idx after the whole packet is built.

Remove si_pm4_set_reg_va and do the same thing for SET_SH_REG.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
2023-06-22 08:35:54 +00:00
Marek Olšák
22f3bcfb5a radeonsi/gfx11: use SET_*_REG_PAIRS_PACKED packets for pm4 states
It can generate all PACKED packets, but only SET_CONTEXT_REG_PAIRS_PACKED
is generated because register shadowing is required by
SET_SH_REG_PAIRS_PACKED*.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
2023-06-22 08:35:54 +00:00
Marek Olšák
1aa99437d3 radeonsi: eliminate redundant TCS user data and RSRC2 register changes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
2023-06-22 08:35:54 +00:00
Marek Olšák
6959493f8c radeonsi: move the only tcs_out_lds_offsets field to vs_state_bits
This removes 1 user data SGPR.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
2023-06-22 08:35:54 +00:00
Marek Olšák
5632d8d1a7 radeonsi: replace tcs_out_lds_layout with nearly identical tes_offchip_addr
tcs_out_lds_layout is basically renamed to tes_offchip_addr in TCS, using
the same variable as TES and also using the same bit layout. The only
difference in the bit layout was that TCS had to mask out the low bits,
which this also removes.

The enums are renamed to *_SGPR_TCS_OFFCHIP_ADDR so as not to conflict
with *_SGPR_TES_OFFCHIP_ADDR, which are in different user data SGPRs.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
2023-06-22 08:35:54 +00:00
Marek Olšák
1b40ab2150 radeonsi: move TCS.gl_PatchVerticesIn into the tcs_offchip_layout SGPR
we'll be able to remove 1 TCS user data SGPR thanks to this

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>
2023-06-22 08:35:54 +00:00
Martin Roukala (né Peres)
b4e2073f04 zink/ci: remove 3 tests from the fails list
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23789>
2023-06-22 08:10:06 +00:00
Martin Roukala (né Peres)
4031ed5c8a amd/ci: temporarily disable some manual jobs that take a long time to run
We are trying to re-enable the valve CI... but doing so runs all the
jobs, including the manual ones.

Since some can take over an hour to run, let's disable them, and
re-enable them in another MR by reverting this commit.

Sorry for the noise!

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23789>
2023-06-22 08:10:06 +00:00
Pavel Ondračka
b4ca45911d nir_opt_algebraic: don't use i32csel without native integer support
Otherwise nir_lower_int_to_float (or specifically nir_gather_ssa_types)
will fail to recognize we already have float constants and converts them
again.

Example from spec/glsl-1.10/execution/vs-loop-array-index-unroll.shader_test
with r300 driver (after enabling has_fused_comp_and_csel).

impl main {
        block block_0:
        /* preds: */
        vec1 32 ssa_0 = load_const (0x00000000 = 0.000000)
        vec4 32 ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32, io location=VERT_ATTRIB_POS slots=1)      /* gl_Vertex */
        vec3 32 ssa_2 = load_const (0x00000000, 0x3e800000, 0x3f800000) = (0.000000, 0.250000, 1.000000)
        vec3 32 ssa_3 = load_const (0x00000000, 0x3f000000, 0x3f800000) = (0.000000, 0.500000, 1.000000)
        vec3 32 ssa_4 = load_const (0x00000000, 0x3f400000, 0x3f800000) = (0.000000, 0.750000, 1.000000)
        vec2 32 ssa_5 = load_const (0x00000000, 0x3f800000) = (0.000000, 1.000000)
        vec1 32 ssa_6 = load_const (0x3f800000 = 1.000000)
        vec1 32 ssa_7 = intrinsic load_ubo_vec4 (ssa_0, ssa_0) (access=0, base=0, component=0)
        vec4 32 ssa_8 = load_const (0x00000000, 0x00000001, 0x00000002, 0x00000003) = (0.000000, 0.000000, 0.000000, 0.000000)
        vec4  1 ssa_9 = ilt ssa_8, ssa_7.xxxx
        vec3 32 ssa_10 = bcsel ssa_9.www, ssa_5.xyy, ssa_4
        vec3 32 ssa_11 = bcsel ssa_9.zzz, ssa_10, ssa_3
        vec3 32 ssa_12 = bcsel ssa_9.yyy, ssa_11, ssa_2
        vec3 32 ssa_15 = i32csel_gt ssa_7.xxx, ssa_12, ssa_6.xxx
        vec4 32 ssa_14 = fsat ssa_15.xyxz
        intrinsic store_output (ssa_14, ssa_0) (base=1, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_COL0 slots=1, xfb(), xfb2())       /* gl_FrontColor */
        intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_POS slots=1, xfb(), xfb2()) /* gl_Position */
        /* succs: block_1 */
        block block_1:
}

and after nir_lower_int_to_float

impl main {
        block block_0:
        /* preds: */
        vec1 32 ssa_0 = load_const (0x00000000 = 0.000000)
        vec4 32 ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32, io location=VERT_ATTRIB_POS slots=1)      /* gl_Vertex */
        vec3 32 ssa_2 = load_const (0x00000000, 0x4e7a0000, 0x4e7e0000) = (0.000000, 1048576000.000000, 1065353216.000000)
        vec3 32 ssa_3 = load_const (0x00000000, 0x4e7c0000, 0x4e7e0000) = (0.000000, 1056964608.000000, 1065353216.000000)
        vec3 32 ssa_4 = load_const (0x00000000, 0x4e7d0000, 0x4e7e0000) = (0.000000, 1061158912.000000, 1065353216.000000)
        vec2 32 ssa_5 = load_const (0x00000000, 0x4e7e0000) = (0.000000, 1065353216.000000)
        vec1 32 ssa_6 = load_const (0x4e7e0000 = 1065353216.000000)
        vec1 32 ssa_7 = intrinsic load_ubo_vec4 (ssa_0, ssa_0) (access=0, base=0, component=0)
        vec4 32 ssa_8 = load_const (0x00000000, 0x3f800000, 0x40000000, 0x40400000) = (0.000000, 1.000000, 2.000000, 3.000000)
        vec4  1 ssa_9 = flt ssa_8, ssa_7.xxxx
        vec3 32 ssa_10 = bcsel ssa_9.www, ssa_5.xyy, ssa_4
        vec3 32 ssa_11 = bcsel ssa_9.zzz, ssa_10, ssa_3
        vec3 32 ssa_12 = bcsel ssa_9.yyy, ssa_11, ssa_2
        vec3 32 ssa_13 = fcsel_gt ssa_7.xxx, ssa_12, ssa_6.xxx
        vec4 32 ssa_14 = fsat ssa_13.xyxz
        intrinsic store_output (ssa_14, ssa_0) (base=1, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_COL0 slots=1, xfb(), xfb2())       /* gl_FrontColor */
        intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_POS slots=1, xfb(), xfb2()) /* gl_Position */
        /* succs: block_1 */
        block block_1:
}

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23704>
2023-06-22 07:25:44 +00:00
Gert Wollny
e853332805 r600/sfn: Add source mod propagation also to fp64 ops
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23754>
2023-06-22 06:31:50 +00:00
Gert Wollny
255eee10ac r600/sfn: Implement fsat for 64 bit ops
Because a plain mov with the fsat modifier doesn't do a proper 64 bit fsat
we either have to propagate the op as modifier to the instruction that
creates the value, or we add a fake op that applies the fsat op, i.e. we
implement the mov as an add_64 with zero as the second value.

Fixes:  0ff3c4bef2
    r600/sfn: drop use of nir source mods

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23754>
2023-06-22 06:31:50 +00:00
Iván Briano
12d86e9822 anv: update conformanceVersion
The Vulkan CTS started generating the list of valid versions the driver
can report as conformant against based on the active branches, and the
1.3.0 branch we were reporting up to now is no longer valid.

Fixes dEQP-VK.api.driver_properties.conformance_version

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23784>
2023-06-22 01:28:32 +00:00
Jesse Natalie
ff52a00553 dzn: Align placed footprints used when copying linear <-> optimal for BC formats
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23662>
2023-06-22 00:57:20 +00:00
Mike Blumenkrantz
402ae3b132 nir/lower_tex: ignore saturate for txf ops
saturate is used for GL_CLAMP emulation, and GL_CLAMP cannot be used
with txf

ref #9226

cc: mesa-stable

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23750>
2023-06-21 23:13:50 +00:00
Mike Blumenkrantz
886b7aaa6b zink: add fastpaths for no-op sampler/view rebinds
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
2023-06-21 22:43:48 +00:00
Mike Blumenkrantz
8125437acd zink: check sampler views pointer before loop
this doesn't need to be checked in every loop iteration

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
2023-06-21 22:43:48 +00:00
Mike Blumenkrantz
58b82d231d zink: don't update tc info directly from cso binds
this somehow becomes expensive at extremely high fps, so defer
until rp begin to check layout change state

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
2023-06-21 22:43:48 +00:00
Mike Blumenkrantz
7b4c1b3a42 zink: track and apply ds3 states only on change
drivers don't do their own state tracking, so ensure the calls are only
made when necessary

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
2023-06-21 22:43:48 +00:00
Mike Blumenkrantz
5dc2d329cb zink: use local screen var in blend state bind
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
2023-06-21 22:43:47 +00:00
Mike Blumenkrantz
2543fc15a1 zink: clean up rp update tracking on dsa bind
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
2023-06-21 22:43:47 +00:00
Mike Blumenkrantz
b65efda508 zink: specialize invalidate_descriptor_state hook for compact mode
the constant flag check here has perf implications at high fps,
so avoid it when possible

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
2023-06-21 22:43:47 +00:00
Mike Blumenkrantz
53542dd120 zink: make invalidate_descriptor_state a ctx hook
this will allow for specialization

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
2023-06-21 22:43:47 +00:00
Mike Blumenkrantz
ad04bd81b9 zink: force inlining for a bunch of functions
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
2023-06-21 22:43:47 +00:00
Mike Blumenkrantz
14bf10c1ad zink: no-op redundant samplemask changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>
2023-06-21 22:43:47 +00:00