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Author SHA1 Message Date
Connor Abbott
293f137d4d freedreno: Disable early preamble on a6xx gen4 
Disable it until someone does more investigation of exactly what needs
to be disabled.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29903>
 2024-06-26 15:16:38 +00:00
Connor Abbott
c42f6597f9 ir3: Make sure constlen includes stc/ldc.k/ldg.k instructions 
nir_opt_preamble sometimes adds useless expressions, in which case we
may have stc instructions and no corresponding use of the constant.
Things can go sideways when these aren't included in the constlen, so
far only observed when earlypreamble is enabled.

Fixes: ccc64b7e00 ("ir3: Plumb through store_uniform_ir3 intrinsic")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29903>
 2024-06-26 15:16:38 +00:00
Matt Coster
536775ee8b docs: List VK_EXT_debug_utils 
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24488>
 2024-06-26 15:07:16 +00:00
Valentine Burley
8cfdc099cd tu: Use the common version of vkQueueBindSparse 
This is implemented in the common runtime. No need to provide a stub here.

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29854>
 2024-06-26 14:38:22 +00:00
Valentine Burley
d882198fc3 tu: Move buffer related code to tu_buffer.cc/h 
More code isolation. Match the structure of the common Vulkan runtime,
NVK and RADV.

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29854>
 2024-06-26 14:38:22 +00:00
Valentine Burley
c0a9b0f8d6 tu: Use the common version of vkGetBufferMemoryRequirements2 
Additionally simplify the code by inlining the logic from
tu_get_buffer_memory_requirements directly into
tu_GetDeviceBufferMemoryRequirements.

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29854>
 2024-06-26 14:38:22 +00:00
Pierre-Eric Pelloux-Prayer
1a06494e65 radeonsi/tests: clarify the output when results changes 
Print up to 10 results that are different from the baseline:

   2 new results:
     * spec@!opengl 1.0@rasterpos,Crash
     * spec@glsl-es-3.00@execution@built-in-functions@vs-packhalf2x16,Fail

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
 2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer
d9f150f18b radeonsi/tests: update tests baseline 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
 2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer
6ec95b990e ac/nir: don't use the compute blit for PIPE_FORMAT_R5G6B5_UNORM 
It breaks spec@arb_pixel_buffer_object@texsubimage array pbo and
spec@arb_pixel_buffer_object@texsubimage pbo with some formats:

72,3,0: test = 140,0,8,255 ref = 148,0,8,255 (comparing 8 bits)
texsubimage failed
  target: GL_TEXTURE_1D_ARRAY
  internal format: GL_R3_G3_B2
  region: 5, 3  116 x 11
72,3,0: test = 140,0,8,255 ref = 148,0,8,255 (comparing 8 bits)
texsubimage failed
  target: GL_TEXTURE_1D_ARRAY
  internal format: GL_RGB5
  region: 33, 3  78 x 11
72,10,0: test = 140,0,41,255 ref = 148,0,41,255 (comparing 8 bits)
texsubimage failed
  target: GL_TEXTURE_1D_ARRAY
  internal format: GL_RGB5_A1
  region: 3, 10  124 x 33
72,19,4: test = 140,65,74,255 ref = 148,65,74,255 (comparing 8 bits)
texsubimage failed
  target: GL_TEXTURE_2D_ARRAY
  internal format: GL_R3_G3_B2
  region: 36, 19  81 x 18
12,36,4: test = 25,66,140,255 ref = 25,66,148,255 (comparing 8 bits)
texsubimage failed
  target: GL_TEXTURE_2D_ARRAY
  internal format: GL_RGB5
  region: 12, 9  30 x 39
72,22,2: test = 140,33,90,255 ref = 148,33,90,255 (comparing 8 bits)
texsubimage failed
  target: GL_TEXTURE_2D_ARRAY
  internal format: GL_RGB5_A1
  region: 39, 22  36 x 37

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
 2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer
c97591b862 radeonsi: add gfx11 workaround for upgraded_depth 
For unknown reasons, this is needed to avoid breaking
a bunch of tests:

   .*tex-miplevel-selection.*
   KHR-GL46.direct_state_access.framebuffers_texture_attachment,Fail
   KHR-GL46.direct_state_access.framebuffers_texture_layer_attachment,Fail
   .*.core.texture_cube_map_array.sampling

These failures were previously hidden by extra flushes in the
blitter that were removed in 969ed851.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
 2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer
abd048124a ac/surface: reject modifiers with retile_dcc and bpe != 32 
radv has a comment in radv_meta_dcc_retile.c:
   * BPE is always 4 at the moment and the rest is derived from the tilemode.
radeonsi has in si_retile_dcc:
   /* We have only 1 variant per bpp for now, so expect 32 bpp. */
   assert(tex->surface.bpe == 4);

This fixes ext_image_dma_buf_import-modifiers for radeonsi.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
 2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer
9d8073a5fd radeonsi/tests: add a shortcut to re-run only failing tests 
'-t baseline' will only run the tests that are marked as failing.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
 2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer
27a841d335 radeonsi/tests: don't match gfx10_3 baseline for gfx10 family 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
 2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer
19e342b877 radeonsi: handle DBG(TEX) after tc_compatible_htile is set 
Otherwise the value printed might be incorrect.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
 2024-06-26 14:02:13 +00:00
Erik Faye-Lund
f4e7204e73 docs: fix bootstrap-extension 
We shouldn't use this extension at all if we're not using the HTML
builder. This should hopefully fix this issue a bit more fundamentally.

This caused issues when using the spelling extension, something I do
locally from time to time.

Fixes: f72033bb70 ("docs: add bootstrap extension")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29888>
 2024-06-26 13:54:13 +00:00
Erik Faye-Lund
18db05d3e6 vulkan/runtime: implementaiton -> implementation 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29890>
 2024-06-26 12:31:00 +00:00
Erik Faye-Lund
3967f8cd84 vulkan/runtime: multiesample -> multisample 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29890>
 2024-06-26 12:31:00 +00:00
Erik Faye-Lund
788d1b5a67 vulkan/runtime: abreviation -> abbreviation 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29890>
 2024-06-26 12:31:00 +00:00
Erik Faye-Lund
947446ade7 vulkan/runtime: initizlie -> initialize 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29890>
 2024-06-26 12:31:00 +00:00
Erik Faye-Lund
a966a11161 vulkan/runtime: tne -> the 
This is clearly a typo.

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29890>
 2024-06-26 12:31:00 +00:00
Karol Herbst
e5bb32da98 rusticl: enable v3d 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
0b85476d86 v3d: never replace a mapped bo 
The application might have a pointer into the mapped bo.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
e5c4ea9323 v3d: fix MAX_GLOBAL_SIZE and MAX_MEM_ALLOC_SIZE 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
6768c81974 v3d: support variable shared memory 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
61b1a14e91 v3d: lower 64 bit ALUs 
Even though rusticl won't advertise support for 64 bit ints, some of the
libclc builtins still use 64 bit operations to lower 32 bit ALU ops.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
7ff96fb5b0 v3d: lower CL alus 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
8f72e60c75 v3d: treat SHADER_KERNEL as SHADER_COMPUTE 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
3889a8e26c v3d: implement gallium APIs for OpenCL support 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
742984a325 broadcom/compiler: handle variable shared memory 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
9bf0b3a112 broadcom/compiler: call nir_lower_64bit_phis 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
4a169a518e broadcom/compiler: implement load_kernel_input 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
caa3872f76 broadcom/compiler: abort on unknown intrinsics 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
f8ab9c0e93 broadcom/compiler: handle up to vec16 load_uniforms 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
e050b13777 broadcom/compiler: try handling 8/16 bit alu operations 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
c7f9cca985 broadcom/compiler: fix iu2f32 for 8 and 16 bit inputs 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
214121e9b0 broadcom/compiler: handle fp16 conversion ops 
As long as fp16 isn't advertized it's not doing much, but it also doesn't
hurt to add them.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
c2ec65eeda broadcom/compiler: add generated v3d_nir_lower_algebraic 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
a8f4ff691b rusticl/kernel/launch: fix global work offsets for 32 bit archs again 
Fixes: bb2453c649 ("rusticl/kernel: move most of the code in launch inside the closure")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
39721a7476 rusticl/mesa/screen: handle get_timestamp not set by driver 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
bb33dbeeaa rusticl/mesa/context: handle clear_buffer not set by driver 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
be4f3c2aa8 rusticl/device: require PIPE_CAP_TEXTURE_SAMPLER_INDEPENDENT for image support 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
0fa4eaf6f6 gallium: add PIPE_CAP_TEXTURE_SAMPLER_INDEPENDENT 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
d5da434851 nir/opt_sink: add load_kernel_input 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
535e617ccd nir/lower_alu: support 8 and 16 bit bit_count 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Daniel Schürmann
c4a38c6583 aco/spill: don't remove spilled phis 
They will be removed during register allocation.

Few changes due to different phi order.
Totals from 14 (0.02% of 79395) affected shaders: (GFX11)

Instrs: 315724 -> 315675 (-0.02%); split: -0.02%, +0.01%
CodeSize: 1673608 -> 1673268 (-0.02%); split: -0.03%, +0.00%
Latency: 3194243 -> 3189025 (-0.16%); split: -0.19%, +0.03%
InvThroughput: 638369 -> 637323 (-0.16%); split: -0.19%, +0.03%
VClause: 5716 -> 5714 (-0.03%)
Copies: 37786 -> 37748 (-0.10%); split: -0.13%, +0.03%
Branches: 10469 -> 10454 (-0.14%); split: -0.16%, +0.02%
VALU: 182498 -> 182454 (-0.02%); split: -0.03%, +0.00%
SALU: 36038 -> 36046 (+0.02%); split: -0.01%, +0.04%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:34 +00:00
Daniel Schürmann
634051f913 aco/live_var_analysis: ignore dead phis 
Since we don't emit code for dead phis, we also don't
have to keep their operands around.

Totals from 44 (0.06% of 79395) affected shaders: (GFX11)

MaxWaves: 648 -> 650 (+0.31%)
Instrs: 449898 -> 449120 (-0.17%); split: -0.18%, +0.00%
CodeSize: 2395000 -> 2389300 (-0.24%); split: -0.24%, +0.00%
VGPRs: 5504 -> 5468 (-0.65%)
Latency: 9005058 -> 9000966 (-0.05%); split: -0.07%, +0.03%
InvThroughput: 2154567 -> 2139095 (-0.72%); split: -0.77%, +0.06%
VClause: 8362 -> 8354 (-0.10%)
SClause: 9135 -> 9134 (-0.01%)
Copies: 60678 -> 60118 (-0.92%); split: -0.93%, +0.01%
Branches: 14379 -> 14385 (+0.04%)
PreSGPRs: 3877 -> 3863 (-0.36%)
PreVGPRs: 6318 -> 6286 (-0.51%)
VALU: 266975 -> 266301 (-0.25%); split: -0.25%, +0.00%
SALU: 52741 -> 52667 (-0.14%); split: -0.15%, +0.01%
VMEM: 16140 -> 16132 (-0.05%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:34 +00:00
Daniel Schürmann
708e1a73f5 aco/live_var_analysis: slightly refactor handling of additional register demand for Operand copies 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:34 +00:00
Daniel Schürmann
5cfa5b784b aco: remove get_demand_before() 
The register demand before executing an instruction is now included
in the instruction's register demand and this function is unused.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:34 +00:00
Daniel Schürmann
09f1c40f2e aco: track and use the live-in register demand per basic block 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:34 +00:00
Daniel Schürmann
001c8caae0 aco: calculate register demand per instruction as maximum necessary to execute the instruction 
Previously, the register demand per instruction was calculated as the number of
live variables in the register file after executing an instruction plus additional
temporary registers, necessary during the execution of the instruction.
With this change, now it also includes all variables which are live right before
executing an instruction, i.e. killed Operands.

Care has been taken so that the invariant

register_demand[idx] = register_demand[idx - 1] - get_temp_registers(prev_instr)
                        + get_live_changes(instr) + get_temp_registers(instr)

still holds.

Slight changes in scheduling:

Totals from 316 (0.40% of 79395) affected shaders: (GFX11)

Instrs: 301329 -> 300777 (-0.18%); split: -0.31%, +0.12%
CodeSize: 1577976 -> 1576204 (-0.11%); split: -0.21%, +0.10%
SpillSGPRs: 448 -> 447 (-0.22%)
Latency: 1736349 -> 1726182 (-0.59%); split: -2.01%, +1.42%
InvThroughput: 243894 -> 243883 (-0.00%); split: -0.03%, +0.03%
VClause: 6134 -> 6280 (+2.38%); split: -1.04%, +3.42%
SClause: 6142 -> 6137 (-0.08%); split: -0.13%, +0.05%
Copies: 14037 -> 14032 (-0.04%); split: -0.56%, +0.52%
Branches: 3284 -> 3283 (-0.03%)
VALU: 182750 -> 182718 (-0.02%); split: -0.04%, +0.03%
SALU: 18522 -> 18538 (+0.09%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:33 +00:00