Commit graph

199241 commits

Author SHA1 Message Date
Qiang Yu
129e37bab6 nir: do not generate b2i64 when driver want to lower it
This is found on GFX12 by:
  KHR-GL43.shader_ballot_tests.ShaderBallotBitmasks

ACO does not support it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32570>
2024-12-16 07:35:07 +00:00
Qiang Yu
12ea316a05 radeonsi: add AMD_FORCE_SHADER_USE_ACO for debug
Narrow down ACO compiler problem to a single shader.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32570>
2024-12-16 07:35:06 +00:00
Qiang Yu
679c450184 util/blake3: add _mesa_blake3_from_printed_string
To convert printed blake3 string back to blake3 hash.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32570>
2024-12-16 07:35:06 +00:00
Qiang Yu
0fd99353a6 radeonsi: disable use_gfx12_xfb_intrinsic when use ACO
ACO does not implement nir_ordered_add_loop_gfx12_amd which is for
LLVM only.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32570>
2024-12-16 07:35:06 +00:00
Qiang Yu
b14cc34415 ac/surf: add more modifiers to gfx12 supported list
OpenGL will export these modifiers for various sized
textures.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32570>
2024-12-16 07:35:06 +00:00
Qiang Yu
b3a218d444 ac/surface/tests: support all block sizes
We are going to add more modifiers.

GFX9 has 4K DCC and non-DCC modifiers while others only have
4K non-DCC modifiers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32570>
2024-12-16 07:35:06 +00:00
Caio Oliveira
93dfe504f2 intel/brw: Add SHADER_OPCODE_READ_FROM_CHANNEL and LIVE_CHANNEL
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32412>
2024-12-14 11:38:14 -08:00
Job Noorman
4d04396531 ir3/validate: print file/line info
This makes it much easier to spot where a validation error comes from as
many assert are similar so difficult to grep for.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32623>
2024-12-14 06:05:26 +00:00
Caio Oliveira
d325de316d intel/brw: Add some tests for new Xe2 register regioning restrictions
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28636>
2024-12-14 02:15:18 +00:00
Caio Oliveira
f308be16a0 intel/brw: Add validation for some Xe2 register regioning restrictions
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28636>
2024-12-14 02:15:18 +00:00
Caio Oliveira
6a5a316312 intel/brw: Extract format enum in EU validation code
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28636>
2024-12-14 02:15:18 +00:00
Caio Oliveira
57b703cec3 intel/brw: Skip some regioning EU validation for Vx1 and VxH modes
Skip the ones that check the VertStride -- which is set to a special
value in those modes.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28636>
2024-12-14 02:15:18 +00:00
Kenneth Graunke
d85d6ad2a5 iris: Tune the BO cache's bucket sizes
With the introduction of the slab allocator, most of our small
allocations now hit that rather than directly hitting the bucket
cache.  Those now show up as 2MB slab allocations from the cache's
perspective.  So, we don't need quite as many buckets.  (Note that
only allocations in IRIS_MEMZONE_OTHER are suballocated today.)

Previously, we had 55 buckets, going from 4KB to 112MB, with sizes
N, N+1/4, N+1/2, N+3/4 for a series of power-of-two N's.

This patch prunes it down to 25 buckets:

   - 4K-4MB => power-of-two sizes only
   - 6MB    => a one-off bucket to reduce waste between 4MB and 8MB
   - 8MB+   => the usual N, N+1/4, N+1/2, N+3/4 system
   - 64MB   => the largest bucket size

In particular, this eliminates the 1.75MB, 2.5MB, 3MB, 3.5MB, and 7MB
buckets in favor of multiples of 2MB.  Allocating multiples of 2MB is
preferable because it allows the kernel to allocate 64KB pages rather
than being stuck using inefficient 4K pages.  And, the amount of waste
from bumping to the next multiple of 2MB isn't huge in that range of
sizes.  We also eliminate buckets larger than 64MB because they're
rarely used, and also the amount of waste from rounding up to the
80/96/112MB buckets can get pretty large.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Fixes: 0b6693a3a1 ("iris: Align fresh BO allocations to 2MB in size")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10219
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32635>
2024-12-13 15:37:09 -08:00
Felix DeGrood
0f46c53b0c anv: Use vfg distribution mode = RR_STRICT for Xe2+
Performance tuning. Round Robin strict faster on Xe2 for some
workloads.

Speedup:
 - Borderlands3-dx11-trace: +4%
 - WolfensteinYoungblood-vk.g6: +1.5%
 - Cyberpunk2077-dx12vk-2160p-ultra: +0.5%

Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32566>
2024-12-13 19:15:48 +00:00
Felix DeGrood
260f3b4444 iris: Use vfg distribution mode = RR_STRICT for Xe2+
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32566>
2024-12-13 19:15:48 +00:00
Deborah Brouwer
3bddf77f61 ci: separate python tests and artifacts
Currently the python-test job runs pytest and then creates python
related artifacts for use by other jobs. But the python-test job isn't
triggered by changes to the python scripts and libraries. Instead, changes
to python scripts and libraries can currently be merged without running
pytest and, if they do generate errors, they will only appear in ci
later when trying to generate the python artifacts.

Add pytest to the existing linting jobs and expand the rules so that it
will be triggered by changes to python scripts and libraries. Remove
pytest from the job that creates artifacts. This will ensure that the
artifacts are still valid while catching script/library errors before they
are merged.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32340>
2024-12-13 10:04:03 -08:00
Deborah Brouwer
90cb87e918 ci: yaml-toml-shell-test: use pyutils container
Currently the yaml-toml-shell-test extends the python-test job to make
use of the python packages available there. But the python-test also
generates artifacts which yaml-toml-shell-test does not need to do.

Instead of extending the python-test job, avoid extra work by just using
the pyutils container directly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32340>
2024-12-13 10:04:03 -08:00
Deborah Brouwer
b6435207ab ci: python-test rename artifacts
The current python-test job creates and compresses python related
artifacts for use by future jobs. The artifacts are currently named
`mesa-python-test` which is somewhat misleading because they are not
needed for testing python scripts or libraries.

Rename the artifacts generated by the python-test job to be more
descriptive of their purpose.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32340>
2024-12-13 10:04:03 -08:00
Deborah Brouwer
dca6310182 ci: debian/x86_64_pyutils remove redundant rules
The debian/x86_64_pyutils job incorporates references to rules from the
python-test and .container jobs, but currently these jobs don't have any
express rules. The .container job does extend jobs that have rules, but
these same rules are already included in debian/x86_64 because it
extends the .debian-container job.

Remove these empty rule references to make debian/x86_64_pyutils more
readable.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32340>
2024-12-13 10:04:03 -08:00
Marek Olšák
c7366985e5 r600: fix a constant buffer memory leak for u_blitter
Fixes: 3d6e44fd - r300,r600,svga: save the FS constant buffer for u_blitter to fix a regression
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12131

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32594>
2024-12-13 16:58:38 +00:00
David Rosca
4ec3f6a0db frontends/va: Stop converting formats in Put/GetImage
This should not do any conversions and instead return error when image
and surface formats don't match.
There was also special case for I420 fourcc which would swap the order
of U/V planes and because of this the plane order of IYUV format was
incorrectly set to YVU in vl_video_buffer.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32605>
2024-12-13 16:19:39 +00:00
David Rosca
df8ee11dc6 gallium/vl: Fix plane order for IYUV format
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32605>
2024-12-13 16:19:39 +00:00
David Rosca
8a20e634ce gallium/vl: Add plane order for Y8_400 format
Also add assert for unhandled format and remove assert for number of
components.

Cc: mesa-stable
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32605>
2024-12-13 16:19:39 +00:00
David Rosca
2ed862c2fe radeonsi/vpe: Silence expected errors with unsupported output format
YUV formats are currently unsupported for output, so we should not
print any errors in case application uses YUV output format.
There is a shader fallback that will be correctly used in this case.
Don't print any vpelib errors unless AMDGPU_SIVPE_LOG_LEVEL is set.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12263
Acked-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32543>
2024-12-13 15:53:48 +00:00
Karol Herbst
a2339542f5 rusticl/util: fix duplicate key detection in Properties::new
We only need to check if the key exist, not the key as a value.

Fixes: efab5cab9f ("rusticl/util: reimplement Properties over Vec of scalars")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32621>
2024-12-13 14:24:03 +00:00
Samuel Pitoiset
1291981ebd radv: mark HAWAII (GFX7) as Vulkan 1.3 conformant
https://www.khronos.org/conformance/adopters/conformant-products#submission_848

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32620>
2024-12-13 13:32:38 +00:00
Christian Gmeiner
fb67ad890a docs: Update perfetto with the latest status
v3d supports PPS counters.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31751>
2024-12-13 12:29:11 +00:00
Christian Gmeiner
ea0784dfb8 perfetto: Add v3d data sources to gpu.cfg
Just like for msm and i915, so it works out-of-the-box.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31751>
2024-12-13 12:29:11 +00:00
Christian Gmeiner
e6d83f1947 perfetto: Add v3d data sources to system.cfg
Just like for msm and i915, so it works out-of-the-box.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31751>
2024-12-13 12:29:11 +00:00
Christian Gmeiner
27771b4d55 pps: Add support for v3d ds
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31751>
2024-12-13 12:29:11 +00:00
Christian Gmeiner
3d2d3b2c10 broadcom: Add perfetto data source
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31751>
2024-12-13 12:29:11 +00:00
Christian Gmeiner
27fb3c549a v3d: Sync v3d_drm.h with drm-misc-next
This pulls in changes based on 8a4b913df427 ("drm/log: Add integer scaling support")
and brings support for the perfmon set global ioctl(..).

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Maíra Canal <mcanal@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31751>
2024-12-13 12:29:11 +00:00
Valentine Burley
f456642501 turnip/ci: Ony increase hangcheck timer for spilling tests on a630
This also allows deleting the baremetal-deqp-test-freedreno-vk
definition.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32588>
2024-12-13 10:15:32 +00:00
Valentine Burley
2b67da4cea freedreno/ci: Drop redundant DEQP_VER
DEQP_VER isn't used with deqp-runner suites.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32588>
2024-12-13 10:15:32 +00:00
Valentine Burley
cea8bafd59 turnip/ci: Update expectations
Decreasing the fractions uncovered some new flakes and fails.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32588>
2024-12-13 10:15:32 +00:00
Valentine Burley
61a9ab27f3 turnip/ci: Remove a630-vk-asan skip
Memory leak detection is currently disabled in the a630-vk-asan
suite, so there's no point in skipping these tests.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32588>
2024-12-13 10:15:32 +00:00
Valentine Burley
31ac69aebd turnip/ci: Adjust some timeouts
Reduce the timeouts for full runs. These values are still quite
conservative.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32588>
2024-12-13 10:15:32 +00:00
Valentine Burley
3602e03428 turnip/ci: Decrease fraction for a630-vk-asan
Not related to the tests_per_group changes, but this has been has
been taking approximately 4 minutes, leaving us some space to run
more tests.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32588>
2024-12-13 10:15:32 +00:00
Valentine Burley
0fb55f7697 turnip/ci: Bump the number of tests per group for a660
Due to the slow startup time of deqp-vk, the previous default of
500 tests per group caused the jobs to run up to twice as slowly
compared to using a higher number of tests per group.

Increase the number of tests per group for all subsets of the
deqp-runner suites, which allows decreasing the fractions.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32588>
2024-12-13 10:15:32 +00:00
Valentine Burley
69aa988eca turnip/ci: Bump the number of tests per group for a630
Due to the slow startup time of deqp-vk, the previous default of
500 tests per group caused the jobs to run up to twice as slowly
compared to using a higher number of tests per group.

Increase the number of tests per group for all subsets of the
deqp-runner suites, which allows decreasing the fractions.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32588>
2024-12-13 10:15:32 +00:00
Valentine Burley
36de4c8fb9 turnip/ci: Bump the number of tests per group for a618
Due to the slow startup time of deqp-vk, the previous default of
500 tests per group caused the jobs to run up to twice as slowly
compared to using a higher number of tests per group.

Increase the number of tests per group for all subsets of the
deqp-runner suites, which allows decreasing the fractions.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32588>
2024-12-13 10:15:32 +00:00
Valentine Burley
680885d57e radv/ci: Convert Valve RADV jobs to deqp-runner suites
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32558>
2024-12-13 09:36:08 +00:00
Erik Faye-Lund
cae4c57b7a panvk/ci: add a few more g52 skips
When I last updated this, some of the jobs had too many tests that took
over 30 seconds to show them all in the output. So I only added the
longest ones. Here's the rest, and with this the skip-list seems correct
for now.

Note that there's a few tests that takes close to 30 seconds, so they
might end up getting pushed across the limit from time to time as well.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32603>
2024-12-13 08:35:04 +00:00
Erik Faye-Lund
ff9f4640c2 panvk/ci: fixup g52 skip sorting
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32603>
2024-12-13 08:35:04 +00:00
Erik Faye-Lund
cbaf3c4849 panvk/ci: correct timeouts as crash
While these timeout when I run them locally,
MESA_VK_ABORT_ON_DEVICE_LOSS ends up turning them into crashes on the
CI. Correct this, so we don't accidentally fail the full job here.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32603>
2024-12-13 08:35:04 +00:00
Sagar Ghuge
d3f9139e49 intel: Use Morton compute walk order
According to HSD 14016252163 if compute shader uses the sample
operation, morton walk order and set the thread group batch size to 4 is
expected to increase sampler cache hit rates by increasing sample
address locality within a subslice.

Rework:
 * Caio: "||" => "&&" for type checking in instr_uses_sampler()
 * Jordan: Use nir's foreach macros rather than
   nir_shader_lower_instructions()

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32430>
2024-12-12 19:56:47 -08:00
Sagar Ghuge
4bd958243d intel/genxml: Update COMPUTE_WALKER_BODY
For PTL, we can have one more additional walk order along with the
"Thread Group Batch Size" field.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32430>
2024-12-12 19:56:47 -08:00
Sagar Ghuge
41eda955af intel/genxml: Drop morton walk field from Xe2
Looks like this one got added accidently for Xe2. Xe2 doesn't support
Morton dispatch walk order.

Thanks to Rohan for bringing up this during review.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32430>
2024-12-12 19:56:47 -08:00
Caio Oliveira
0af8133f09 intel/executor: Add example using scalar register and send gather
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32236>
2024-12-13 02:18:15 +00:00
Caio Oliveira
5420c027e6 intel/brw: Add validation for ARF scalar register
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32236>
2024-12-13 02:18:15 +00:00