Commit graph

61498 commits

Author SHA1 Message Date
Qiang Yu
07fcb4aa19 radeonsi: remove param type check in wrapper function
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24204>
2023-07-24 01:49:21 +00:00
Qiang Yu
7ebf667360 radeonsi: move vertex shader vb desc input sgpr args to last
ACO use same args for merged shader stages, but vb desc input sgpr args
is not present when second stage of merged shader. In order to share
same shaders args, move it to last so other args have same index.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24204>
2023-07-24 01:49:21 +00:00
Qiang Yu
a4b4f9a62a radeonsi: simplify si_build_wrapper_function
We only need it to merge LS/HS or ES/GS now, prolog and epilog have
been lowered in nir already. So we just need to handle two parts and
they are sure to be first and second stage of a merged shader.

This also remove the needs SGPRs must be before VGPRs, which is required
by following commits to move some SGPRs after VGPRs.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24204>
2023-07-24 01:49:21 +00:00
Qiang Yu
d9f7902afb radeonsi: init aco shader info for merged LS/HS
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24204>
2023-07-24 01:49:21 +00:00
Qiang Yu
7daa0857c0 radeonsi: extract si_get_prev_stage_nir_shader to be shared with aco
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24204>
2023-07-24 01:49:21 +00:00
Qiang Yu
ec17cc345f radeonsi: aco does not pass LS outputs to HS by arg
aco has global input/output variables for this.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24204>
2023-07-24 01:49:21 +00:00
Konstantin Seurer
01266f8119 llvmpipe: Fix compiling with LP_USE_TEXTURE_CACHE
Fixes: 36eb75d ("llvmpipe: move to common sampler/image binding code")
Closes: #9359

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24243>
2023-07-23 19:11:40 +00:00
Thomas H.P. Andersen
d84d5ff0ce tgsi: drop two unused functions
Removes:
* tgsi_util_get_src_from_ind
* tgsi_full_src_register_from_dst

The last usage of these got removed in !24175

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24283>
2023-07-22 02:04:57 +00:00
Dave Airlie
2b03938f27 gallivm: fix atomic global temporary storage.
Fixes regression on llvm15 with
piglit tests/cl/program/execute/builtin/atomic/atomic_xchg-global.cl

Fixes: f281290005 ("gallivm: Fix atomic_global types")
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24267>
2023-07-21 20:48:16 +00:00
Charmaine Lee
9c17d9df43 svga: set clear_texture to NULL for vgpu9
With PIPE_CAP_CLEAR_TEXTURE removed, we need to set clear_texture to NULL
on svga vgpu9 device so it can use the fallback path.

Fixes: a1eabeff66 ("gallium: remove PIPE_CAP_CLEAR_TEXTURE")

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24264>
2023-07-21 17:36:31 +00:00
Yiwei Zhang
8cb7bab341 lvp: avoid reading immutable sampler from desc write info
Lavapipe has switched to layer push descriptor support atop descriptor
updates internally since 12a7fc51c7, so
it must skip retrieving immutable samplers from the write info even if
the update call itself is blessed by the spec to not hit that case.

Fixes: 12a7fc51c7 ("lavapipe: Rework descriptor handling")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24263>
2023-07-21 17:11:26 +00:00
Connor Abbott
c75bf084d0 tu, freedreno/a6xx: Remove has_ccu_flush_bug
Based on the previous commit, this isn't actually a bug and is expected
behavior. Turnip should already be handling it correctly for user
flushes, we just have to make sure to handle it for flushes we insert
ourselves in turnip and freedreno.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24162>
2023-07-21 16:02:50 +00:00
David Rosca
0bd9ab232b gallium/auxiliary/vl: Fix RGB->YCbCr full range matrix
Also rename it to bt_709_rev_full as there already
is bt_709 which is used for YCbCr->RGB.

Fixes: 8a21efce3a ("frontends/va: Add postproc support for converting to full range")

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24238>
2023-07-21 15:16:26 +00:00
Sathishkumar S
0195e1204b radeonsi/vcn: num bs_bufs must be proportional to num jpeg engines
using limited number of bs buffers constraints the simultaneous
use of all available jpeg engines especially when count is lesser than
that of the available engines. make sure the number of buffers
available are more than or equal to the number of jpeg engines on the asic.

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24240>
2023-07-21 14:42:09 +00:00
Sathishkumar S
47a9d01641 radeonsi/vcn: support variable number of bs_bufs
add support to use variable number of bitstream buffers for decode

v2: remove the always true if condition (CI report)

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24240>
2023-07-21 14:42:09 +00:00
Alyssa Rosenzweig
03b2c34793 nir: Remove register arrays
Nothing produces them any more, so remove them from NIR. This massively reduces
the size of nir_src, which should improve performance all over.

nir_src size reduced from 56 bytes -> 40 bytes (pahole results on arm64, x86_64
should be similar.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24253>
2023-07-21 11:25:49 +00:00
Alyssa Rosenzweig
1466014184 nir: Rename lower_locals_to_reg_intrinsics back
The short name is freed up.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24253>
2023-07-21 11:25:49 +00:00
Rohan Garg
e7e7042093 anv,iris: program the maximum number of threads on compute queue init
Fixes: 90a39cac87 ("intel/blorp: Emit compute program based on BLORP_BATCH_USE_COMPUTE")
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23934>
2023-07-21 10:46:08 +00:00
Christian Gmeiner
5a95280748 etnaviv: nir: lower nir_texop_txs
Non of the GPU models know at this time have hardware support to
retrieve the dimensions of a level of a texture. Do almost the
same as the binary blob and store the needed values as uniforms.

Passes dEQP-GLES3.functional.shaders.texture_functions.texturesize.*

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24217>
2023-07-21 08:52:03 +00:00
Christian Gmeiner
88f399b651 etnaviv: nir: support intrinsic used for txs lowering
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24217>
2023-07-21 08:52:03 +00:00
Christian Gmeiner
65ffa5b0b8 etnaviv: move nir texture lowerings into one pass
This is just a prep commit to keep all texture related
lowerings in one c file.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24217>
2023-07-21 08:52:03 +00:00
M Henning
340df42977 nouveau: Delete the nouveau_compiler tool
It's TGSI only.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>
2023-07-21 02:40:36 +00:00
M Henning
c631635f43 nouveau: Drop tgsi support from nv50_ir_prog_info
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>
2023-07-21 02:40:35 +00:00
M Henning
9178b049cc nv50: Keep nir directly in nv50_program
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>
2023-07-21 02:40:35 +00:00
M Henning
d00d967399 nvc0: Keep nir directly in nvc0_program
instead of under pipe_shader_state.

This makes it obvious that we never produce tgsi shaders since
c3cbe610 "nouveau: Delete the NV50_PROG_USE_TGSI env var."

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>
2023-07-21 02:40:35 +00:00
Mike Blumenkrantz
88bf4b61af zink: emit SpvCapabilitySampleMaskPostDepthCoverage with SpvExecutionModePostDepthCoverage
can't have one without the other

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24183>
2023-07-21 01:28:56 +00:00
Mike Blumenkrantz
d744bb5bfc zink: be even dumber about buffer refs when replacing storage
these extra checks can cause issues when multiple contexts and transfer
ops are involved

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24141>
2023-07-21 01:01:04 +00:00
Karol Herbst
23795dc318 nvc0: fix num_gprs for Volta+
Overallocating by 2 gprs for ugprs is a wild guess by me. It does make
sense though as each subgroup shares 64 ugprs and that's 2 per thread.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24261>
2023-07-20 23:19:58 +00:00
Karol Herbst
fa8634388b llvmpipe: enable system SVM
The API bits are already implemented in clover and rusticl and by
definition a CPU driver implements SVM.

This should allow anybody to work on proper SyCL/CHIP-SPV support for
rusticl running llvmpipe.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24092>
2023-07-20 23:00:24 +00:00
Karol Herbst
44e652af9a rusticl/mesa: make svm_migrate optional
It's just a hint and drivers might want to ignore implementing it for now.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24092>
2023-07-20 23:00:24 +00:00
Nanley Chery
d9bdffa708 intel: Describe modifier compression with booleans
Replace the aux_usage field with two booleans: one for render
compression and one for media compression.

This more accurately describes how CCS_E is used on gfx12. On those
platforms, the FCV feature may be enabled or disabled, but ISL's
modifier table has been using the FCV aux-usage for every gfx12 render
compression modifier. Instead, set the newly-added render compression
boolean to true.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:27 +00:00
Nanley Chery
37068e8aaf iris: Swap stencil and modifier aux assignment order
Makes the next patch clearer.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Nanley Chery
2d7fc325d6 crocus: Delete modifier with aux code
Modifiers with compression are not supported.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Nanley Chery
5568970d63 iris: Reduce accesses of mod_info->aux_usage
This field will be replaced in an upcoming patch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Nanley Chery
c042eb653d iris: Remap DRM_FORMAT_MOD_INVALID more often during import
We'd eventually like to use an ISL helper that doesn't support
DRM_FORMAT_MOD_INVALID. Prepare for this by replacing the invalid value
with the modifier associated with the BO's tiling in more cases.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Marek Olšák
54f18b5000 radeonsi: fix a CDNA regression breaking compute
reported internally

Fixes: 315231b5a5 - radeonsi: eliminate redundant compute SH register changes

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24169>
2023-07-20 18:42:56 +00:00
Alyssa Rosenzweig
950a0b6a63 ir2: Switch to nir_legacy
Addresses a2xx portion of #9051.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24118>
2023-07-20 15:50:54 +00:00
Alyssa Rosenzweig
ad214fcaf7 asahi: Advertise Z16_UNORM
This works (on the downstream kernel, anyway).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:29 +00:00
Alyssa Rosenzweig
0197d46b34 asahi: Execute preambles for background programs
This will be useful when spilling render targets.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:29 +00:00
Alyssa Rosenzweig
9fbe2fdea0 asahi: Offset clear colour uniform by 4
Frees up u0_u1 for a bindless base address which will make render target
spilling easier to implement.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:29 +00:00
Alyssa Rosenzweig
0597c100cc asahi: Ignore spilled render targets for background load
Nothing to reload.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:29 +00:00
Alyssa Rosenzweig
ff16397912 asahi: Lower tilebuffer access for spilled RTs
Conceptually similar, we just don't have the tilebuffer available this time.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
46b5406483 asahi: Ignore spilled render targets with partial renders
Partial renders exist to the spill the tilebuffer to memory, there's nothing to
do if it's already spilled (and would just waste memory bandwidth and create a
feedback loop).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
17e10499b9 asahi: Extract sampler_view_for_surface
We'll reuse this logic for the spilled RT case.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
02b1ddeca6 asahi,agx: Fix txf sampler
Bizarrely, the clamps/wrap modes are respected so we need to set them
appropriately for correct out-of-bounds behaviour (returning all zero). That in
turn means we can't use whatever sampler is already there, instead we need to
allocate a dedicated sampler just for txf. Good news is we have an extra sampler
state register available for the purpose.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
dfea028aa2 asahi: Use nir_lower_robust_access
This makes images robust as required by the OpenGL ES spec.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
2ebdd5fd12 asahi: Extend PBE packing for image support
We need to support arrayed images and sRGB images, which are hardware. For
atomics, we need to pack the augmented software data structure. Finally, we need
to support buffer images. Like their texture counterparts, these get lowered to
2D images.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Asahi Lina
0dc819f284 asahi: Add extra CDM header block for G14X
Looks like we finally found our first properly divergent codepath.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
42fbbd2a73 asahi: Forbid 2D Linear with images
There's no known use case, so forbidding this reduces the combinatorics required
in the texture atomic lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
4e53da7265 asahi: Don't restrict sampler views
We now emulate an infinitely large binding table with bindless, so the sky is
the limit for this CAP. Note we still have the limit for samplers, so this
probably doesn't do anything for OpenGL.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00