Commit graph

5405 commits

Author SHA1 Message Date
Jason Ekstrand
c811af767e anv/so_memcpy: Don't consider src/dst_offset when computing block size
The only thing that matters is the size since we never specify any
offsets in terms of blocks.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-09-19 09:38:04 -05:00
Jason Ekstrand
67094e11e9 anv/query: Add an emit_srm helper
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-09-17 02:57:21 -05:00
Jason Ekstrand
40149441b8 anv: Add a mi_memset and use it for zeroing queries
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-09-17 02:57:21 -05:00
Jason Ekstrand
b11e9b5ffe anv/query: Use anv_address everywhere
Instead of passing around BOs and offsets, use addresses which are anv's
GPU equivalent of pointers.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-09-17 02:57:21 -05:00
Jason Ekstrand
07e214f1ce anv/query: Write both dwords in emit_zero_queries
Each query slot is a uint64_t and we were only zeroing half of it.

Fixes: 7ec6e4e689 "anv/query: implement multiview interactions"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-09-17 02:57:21 -05:00
Jason Ekstrand
c0420a62c9 anv/query: Increment an index while writing results
Instead of computing an index at the end which we hope maps to the
number of things written, just count the number of things as we go.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-09-17 02:57:21 -05:00
Ian Romanick
df9dbc03d3 i965/fs: Don't propagate conditional modifiers from integer compares to adds
No shader-db changes on any Intel platform... which probably explains
why no bugs have been bisected to this problem since it landed in Mesa
18.1. :( The commit mentioned below is in 18.2, so 18.1 would need a
slightly different fix (due to code refactoring).

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Fixes: 77f269bb56 "i965/fs: Refactor propagation of conditional modifiers from compares to adds"
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> (reviewed the original patch)
Cc: Matt Turner <mattst88@gmail.com> (reviewed the original patch)
2018-09-17 00:38:22 -07:00
Caio Marcelo de Oliveira Filho
f9d25f630c anv/memcpy: fix build after starting to use addresses
The offsets now come from the anv_address, these references were not
updated and using the old variable.

Fixes: e1ab834557 "anv/memcpy: Use addresses instead of bo+offset"
Tested-by: Clayton Craft <clayton.a.craft@intel.com>
2018-09-14 21:45:50 -07:00
Jason Ekstrand
d6a73824bd anv/cmd_buffer: Take an address in emit_lrm
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-14 22:12:11 -05:00
Jason Ekstrand
e1ab834557 anv/memcpy: Use addresses instead of bo+offset
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-14 22:12:11 -05:00
Jason Ekstrand
90b46f6c17 anv/so_memcpy: Use the correct SO_BUFFER size on gen8+
This shouldn't matter as we'll never write OOB anyway but we may as well
get it right.  It's supposed to be in dwords - 1.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2018-09-14 22:12:11 -05:00
Jason Ekstrand
1a263b377c anv: Silence a couple compiler warnings
[63/93] Compiling C object 'src/intel/vulkan/...intel@vulkan@@anv_common@sta/anv_device.c.o'.
../src/intel/vulkan/anv_device.c:685:30: warning: passing 'const char *' to parameter of type 'void *' discards qualifiers [-Wincompatible-pointer-types-discards-qualifiers]
   vk_free(&instance->alloc, instance->app_info.app_name);
                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~
../src/vulkan/util/vk_alloc.h:62:51: note: passing argument to parameter 'data' here
vk_free(const VkAllocationCallbacks *alloc, void *data)
                                                  ^
../src/intel/vulkan/anv_device.c:686:30: warning: passing 'const char *' to parameter of type 'void *' discards qualifiers [-Wincompatible-pointer-types-discards-qualifiers]
   vk_free(&instance->alloc, instance->app_info.engine_name);
                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../src/vulkan/util/vk_alloc.h:62:51: note: passing argument to parameter 'data' here
vk_free(const VkAllocationCallbacks *alloc, void *data)
                                                  ^
[65/93] Compiling C object 'src/intel/vulkan/...ommon@sta/anv_nir_apply_pipeline_layout.c.o'.
../src/intel/vulkan/anv_nir_apply_pipeline_layout.c:519:13: warning: unused variable 'image_uniform' [-Wunused-variable]
   unsigned image_uniform;

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-09-12 21:20:27 -05:00
Tapani Pälli
30580640f2 intel/tools: fix initial position of window in aubinator viewer
Currently position is set before widgets are sized by gtk and
calculation can get wrong results where window is positioned
offscreen. Patch fixes this by setting aubfile window position
as 0,0 only when size_allocate has been called to the widget.

Now window is always positioned to 0,0 if imgui.ini is missing.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-09-12 11:43:21 +03:00
Jason Ekstrand
6f00785765 anv: Support v3 of VK_EXT_vertex_attribute_divisor
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-09-10 13:45:32 -05:00
Jason Ekstrand
465e5a868c anv: Clamp scissors to the framebuffer boundary
The Vulkan 1.1.81 spec says:

    "It is legal for offset.x + extent.width or offset.y + extent.height
    to exceed the dimensions of the framebuffer - the scissor test still
    applies as defined above. Rasterization does not produce fragments
    outside of the framebuffer, so such fragments never have the scissor
    test performed on them."

Elsewhere, the Vulkan 1.1.81 spec says:

    "The application must ensure (using scissor if necessary) that all
    rendering is contained within the render area, otherwise the pixels
    outside of the render area become undefined and shader side effects
    may occur for fragments outside the render area. The render area
    must be contained within the framebuffer dimensions."

Unfortunately, there's some room for interpretation here as to what the
consequences are of having the render area set to exactly the
framebuffer dimensions and having a scissor that is larger than the
framebuffer.  Given that GL and other APIs provide automatic clipping to
the framebuffer, it makes sense that applications would assume that
Vulkan does this as well.  It costs us very little to play it safe and
just clamp client-provided scissors to the framebuffer dimensions.
Fortunately, the user is required to provide us with at least one
scissor so we don't need to handle the case where they don't.

Fixes: fb2a5ceb32 "anv: Emit DRAWING_RECTANGLE once at driver..."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-09-07 15:19:02 -05:00
Jason Ekstrand
b08b4b2b25 anv: Disable the vertex cache when tessellating on SKL GT4
I have no idea if I'm correct about what's going wrong or if this is the
correct fix.  However, in my multiple weeks of banging my head on this
hang, a VUE reference counting bug seems to match all the symptoms and
it definitely fixes the hang.

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107280
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-09-07 15:19:02 -05:00
Jason Ekstrand
5dee89438a anv: Implement a VF cache invalidate workaround
Known to fix nothing whatsoever but it's in the docs.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-09-07 15:19:02 -05:00
Jason Ekstrand
c643c5e18d anv: Re-emit vertex buffers when the pipeline changes
Some of the bits of VERTEX_BUFFER_STATE such as access type, instance
data step rate, and pitch come from the pipeline.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-09-07 15:19:02 -05:00
Dylan Baker
8396043f30 Replace uses of _mesa_bitcount with util_bitcount
and _mesa_bitcount_64 with util_bitcount_64. This fixes a build problem
in nir for platforms that don't have popcount or popcountll, such as
32bit msvc.

v2: - Fix additional uses of _mesa_bitcount added after this was
      originally written

Acked-by: Eric Engestrom <eric.engestrom@intel.com> (v1)
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-09-07 10:21:26 -07:00
Lionel Landwerlin
69874e9a6a intel/genxml: turn SLM Enable bit into boolean
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-09-07 14:46:20 +01:00
Sergii Romantsov
97fcccb25e i965/tools: 32bit compilation with meson
Building of 32bit mesa with meson causes issue:
"implicit declaration of function ‘__builtin_ia32_clflush’".
Fixed by adding msse2 compilation flag.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107843
Fixes: 314879f7fe (i965: Fix asynchronous mappings on !LLC platforms.)
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-09-07 13:46:48 +01:00
Sergii Romantsov
d709f12792 intel: compiler option msse2 and mstackrealign
Seems in case of 32-bit library, usage of msse2 makes
some stack corruption or incorrect instructions.
Usage with mstackrealign fixes that case.

v2: Fixed meson.

v3: Definition of c_sse2_args moved on the top (L.Landwerlin).
    Added mstackrealign for Android's mks where msee4.1 is used.

v4: Added for Vulkan also.

v5: Commit message correction.

CC: <mesa-stable@lists.freedesktop.org>
Fixes: 6b05c080f2 (i965: Compile with -msse3)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107779
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-09-07 13:45:46 +01:00
Jason Ekstrand
7b26741806 anv/pipeline: Only consider double elements which actually exist
The brw_vs_prog_data::double_inputs_read field comes directly from
shader_info::double_inputs which may contain inputs which are not
actually read.  Instead of using it directly, AND it with inputs_read
which is only things which are read.  Otherwise, we may end up
subtracting too many elements when computing elem_count.

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103241
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-09-06 16:07:50 -05:00
Jason Ekstrand
44ec31cd75 nir: Drop the vs_inputs_dual_locations option
It was very inconsistently handled; the only things that made use of it
were glsl_to_nir, glspirv, and nir_gather_info.  In particular,
nir_lower_io completely ignored it so anyone using nir_lower_io on
64-bit vertex attributes was going to be in for a shock.  Also, as of
the previous commit, it's set by every driver that supports 64-bit
vertex attributes.  There's no longer any reason to have it be an option
so let's just delete it.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-09-06 16:07:50 -05:00
Eric Engestrom
07ff56791d intel/compiler: remove unused get_image_base_type()
Unused since 09f1de97a7 "anv,i965: Lower away image derefs in
the driver".

Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2018-09-06 15:22:24 +01:00
Lionel Landwerlin
2dce1175c1 Revert "i965/tools: 32bit compilation with meson"
This reverts commit 4aec44c0d9.

Unfortunately this patch needed a another one to be committed first.
2018-09-06 12:25:07 +01:00
Sergii Romantsov
4aec44c0d9 i965/tools: 32bit compilation with meson
Building of 32bit mesa with meson causes issue:
"implicit declaration of function ‘__builtin_ia32_clflush’".
Fixed by adding msse2 compilation flag.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107843
Fixes: 314879f7fe (i965: Fix asynchronous mappings on !LLC platforms.)
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-09-06 11:55:57 +01:00
Alejandro Piñeiro
4e1f8d82c2 i965/fs: include multisamplers on image_intrinsic_coord_components
This is the second patch needed to fix the following piglit tests:

   tests/spec/arb_gl_spirv/linker/uniform/multisampler.shader_test
   tests/spec/arb_gl_spirv/linker/uniform/multisampler-array.shader_test

Although in this case it doesn't affect so many borrowed tests, as
there aren't too many tests using multisamplers on Intel.

It is worth to note that this patch is also needed when those tests
are run on GLSL mode (using the --glsl option). Although most Intel
drivers would not be able to run/execute tests using multisamplers, as
GL_MAX_IMAGE_SAMPLES is zero, technically those tests are expected to
link correctly, so linking tests should pass.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-09-05 17:02:28 +02:00
Alejandro Piñeiro
2a6182fe06 intel/compiler: rename brw_nir_lower_glsl_images
To brw_nir_lower_gl_images, as it will be also used on the
ARB_gl_spirv codepath, that doesn't involves GLSL at all. So the
lowering is about images following the OpenGL semantics. In any case
"brw_nir_lower_opengl_images" seemed too long to me, so I just used
gl. That shortening is already used on other parts of the code.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-09-05 17:02:28 +02:00
Jason Ekstrand
67571ae796 intel/compiler: Remove redundant nir_remove_dead_variables call
As of 07a2098a70, brw_nir_optimize calls nir_remove_dead_variables as
the last optimization.  Doing it again is just pointless.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-09-04 09:03:16 -05:00
Lionel Landwerlin
07a2098a70 intel: compiler: remove dead local variables at optimization pass
We're hitting an assert in gfxbench because one of the local variable
is a sampler (according to Jason this isn't valid) :

testfw_app: ../src/compiler/nir_types.cpp:551: void glsl_get_natural_size_align_bytes(const glsl_type*, unsigned int*, unsigned int*): Assertion `!"type does not have a natural size"' failed.

Since this particular variable isn't used, it can be eliminated by
removing unused local variables at the end of the optimization loop.
This makes sense also for valid local variables.

v2: Move additional local variable removal out of optimization loop,
    but before large constant removal (Jason/Lionel)

v3: Move the removal at the end of brw_nir_optimize()

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107806
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-09-03 17:24:19 +01:00
Andrii Simiklit
095600dad6 intel/decoder: fix the possible out of bounds group_iter
The "gen_group_get_length" function can return a negative value
and it can lead to the out of bounds group_iter.

v2: printing of "unknown command type" was added
v3: just the asserts are added

Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-09-03 11:14:30 +01:00
Jason Ekstrand
2ad9917e18 anv/blorp: Fix a comment as per Nanley's review feedback
This accidentally didn't make it into 62378c5e9e
2018-09-01 09:12:08 -05:00
Jason Ekstrand
62378c5e9e anv/blorp: Do more flushing around HiZ clears
We make the flush after a HiZ clear unconditional and add a flush/stall
before the clear as well.

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107760
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2018-09-01 09:08:36 -05:00
Ian Romanick
82530ce1b5 i965/vec4: Clamp indirect tes input array reads with 0x0fffffff
Page 190 of "Volume 7: 3D Media GPGPU Engine (Haswell)" says the valid
range of the offset is [0, 0FFFFFFFh].

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
2018-09-01 00:23:45 -07:00
Ian Romanick
75666605c9 i965/vec4: Correctly handle uniform sources in generate_tes_add_indirect_urb_offset
Fixes failure in the new piglit test
tes-patch-input-array-vec2-index-invalid-rd.shader_test.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
2018-09-01 00:23:43 -07:00
Rodrigo Vivi
e8c42ed4ab intel: Introducing Amber Lake platform
Amber Lake uses the same gen graphics as Kaby Lake, including a id
that were previously marked as reserved on Kaby Lake, but that
now is moved to AML page.

This follows the ids and approach used on kernel's commit
e364672477a1 ("drm/i915/aml: Introducing Amber Lake platform")

Reported-by: Timo Aaltonen <timo.aaltonen@canonical.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-08-31 13:57:52 -07:00
Rodrigo Vivi
886a048feb intel: aubinator: Adding missed platforms to the error message.
Many new platforms got added to gen_device_name_to_pci_device_id()
but the error message inside aubinator didn't reflected those
changes. So syncing on the same order to be sure that we are not
missing any now.

Cc: Anuj Phogat <anuj.phogat@gmail.com>
Cc: Matt Turner <mattst88@gmail.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-08-31 13:57:41 -07:00
Kenneth Graunke
b147254d36 Revert "intel/tools/aubwrite: Always use physical addresses for traces."
This reverts commit f8cfc77660.

This appears to break intel_dump_gpu for Gen9 systems - I can load them
in the simulator, but nothing happens.  Reverting the patch makes the
simulator properly execute our commands and shaders again.
2018-08-30 14:36:28 -07:00
Jason Ekstrand
a0f18f2142 intel/nir: Lowering image loads and stores trashes all metadata
This fixes the GL_ARB_fragment_shader_interlock piglit test on gen8
platforms where the lack of metadata dirtying was causing another pass
to accidentally delete a much needed loop.

https://bugs.freedesktop.org/show_bug.cgi?id=107745
Fixes: 37f7983bcc "intel/compiler: Do image load/store lowering..."
Jason Ekstrand <jason@jlekstrand.net> writes:
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-30 14:06:31 -05:00
Jason Ekstrand
d8033d4083 intel/compiler: Remove surface_idx from brw_image_param
Now that the drivers are lowering to surface indices themselves, we no
longer need to push the surface index into the shader.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-08-29 14:04:03 -05:00
Jason Ekstrand
3cbc02e469 intel: Use TXS for image_size when we have a typed surface
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-08-29 14:04:03 -05:00
Jason Ekstrand
09f1de97a7 anv,i965: Lower away image derefs in the driver
Previously, the back-end compiler turn image access into magic uniform
reads and there was a complex contract between back-end compiler and
driver about setting up and filling out those params.  As of this
commit, both drivers now lower image_deref_load_param_intel intrinsics
to load_uniform intrinsics controlled by the driver and lower the other
image_deref_* intrinsics to image_* intrinsics which take an actual
binding table index.  There are still "magic" uniforms but they are now
added and controlled entirely by the driver and that contract no longer
spans components.

This also has the side-effect of making most image use compile-time
binding table indices.  Previously, all image access pulled the binding
table index from a uniform.  Part of the reason for this was that the
magic uniforms made it difficult to decouple binding table indices from
the uniforms and, since they are indexed completely differently
(especially in Vulkan), it was hard to pull them apart.  Now that the
driver is handling both, it's trivial to decouple the two and provide
actual binding table indices.

Shader-db results on Kaby Lake:

    total instructions in shared programs: 15166872 -> 15164293 (-0.02%)
    instructions in affected programs: 115834 -> 113255 (-2.23%)
    helped: 191
    HURT: 0

    total cycles in shared programs: 571311495 -> 571196465 (-0.02%)
    cycles in affected programs: 4757115 -> 4642085 (-2.42%)
    helped: 73
    HURT: 67

    total spills in shared programs: 10951 -> 10926 (-0.23%)
    spills in affected programs: 742 -> 717 (-3.37%)
    helped: 7
    HURT: 0

    total fills in shared programs: 22226 -> 22201 (-0.11%)
    fills in affected programs: 1146 -> 1121 (-2.18%)
    helped: 7
    HURT: 0

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-08-29 14:04:03 -05:00
Jason Ekstrand
3942943819 nir: Use a bitfield for image access qualifiers
This commit expands the current memory access enum to contain the extra
two bits provided for images.  We choose to follow the SPIR-V convention
of NonReadable and NonWriteable because readonly implies that you *can*
read so readonly + writeonly doesn't make as much sense as NonReadable +
NonWriteable.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-08-29 14:04:02 -05:00
Jason Ekstrand
4289143899 intel/compiler: Use two components for 1D array image sizes
Having the array length component stored in .z was a small convenience
for the ISL image param filling code and an annoyance in the NIR
lowering code.  The only convenience of treating 1D arrays like 2D
arrays in the lowering code is in the address calculation code so let's
put all the complexity there as well.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-08-29 14:04:02 -05:00
Jason Ekstrand
b1c414ef28 isl: Use the view array length for the image size
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-08-29 14:04:02 -05:00
Jason Ekstrand
37f7983bcc intel/compiler: Do image load/store lowering to NIR
This commit moves our storage image format conversion codegen into NIR
instead of doing it in the back-end.  This has the advantage of letting
us run it through NIR's optimizer which is pretty effective at shrinking
things down.  In the common case of rgba8, the number of instructions
emitted after NIR is done with it is half of what it was with the
lowering happening in the back-end.  On the downside, the back-end's
lowering is able to directly use predicates and the NIR lowering has to
use IFs.

Shader-db results on Kaby Lake:

    total instructions in shared programs: 15166910 -> 15166872 (<.01%)
    instructions in affected programs: 5895 -> 5857 (-0.64%)
    helped: 15
    HURT: 0

Clearly, we don't have that much image_load_store happening in the
shaders in shader-db....

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-08-29 14:04:02 -05:00
Jason Ekstrand
f2d0a2b110 anv/pipeline: Remove dead image loads in lower_input_attacnments
Dead code will get rid of them eventually but it's better if they're
just gone so we guarantee they won't trip up later passes.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-08-29 14:04:02 -05:00
Jason Ekstrand
152fdeddbb nir/format_convert: Rename nir_format_bitcast_uint_vec
We have a name for that, it's called a uvec.  This just makes the
function name a bit shorter.  While we're here, we also add an assert
for one of the assumptions this function makes.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-08-29 14:04:02 -05:00
Sagar Ghuge
40fc4b5acd intel/tools: new i965_disasm tool
Adds a new i965 instruction disassemble tool

v2: 1) fix a few nits (Matt Turner)
    2) Remove i965_disasm header (Matt Turner)

v3: 1) Redirect output to correct file descriptors (Matt Turner)
    2) Refactor code (Matt Turner)
    3) Use better formatting style (Matt Turner)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
2018-08-29 11:19:55 -07:00