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Author SHA1 Message Date
Lionel Landwerlin
034a1cdb58 anv: disable protected content around surface state copies 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 794b0496e9 ("anv: enable protected memory")
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26540>
 2024-04-05 09:07:21 +03:00
Lionel Landwerlin
27a3771227 anv: pull surface state copies for secondary in one loop 
It'll be easier for the next commit.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26540>
 2024-04-05 09:07:21 +03:00
Lionel Landwerlin
07bf480856 anv: fix protected memory allocations 
Using the wrong flag field...

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 5f2c77a10a ("anv: handle protected memory allocation")
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26540>
 2024-04-05 09:07:21 +03:00
Ian Romanick
0e817ba548 intel/brw/xe2+: Implement Wa 22016140776 
HF sources to math instructions cannot be scalar. This is very similar
to an old Gfx6 restriction on POW, so let's fix it in a similar way.

As an extra bit of saftey, lower any occurances that might slip through
in brw_fs_lower_regioning.

The primary change is to prevent copy propagation from violating the
restriction. With that change, nothing should be able to generate these
invalid source strides. The modification to fs_visitor::validate should
detect potential problems sooner rather than later.

Previous attempts to implement this Wa when emitting the math
instruction (in brw_eu_emit.c gfx6_math) didn't work for several
reasons. The lowering happens after the SWSB pass, so the scoreboarding
was incorrect (thanks to Curro for finding that). In addition, the
lowering happens after register allocation, so it's impossible to
allocate a non-scalar register to expand the scalar value.

Fixes 113 tests in the dEQP-VK.spirv_assembly.* group on LNL.

v2: Add changes to brw_fs_lower_regioning. Suggested by Curro.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28480>
 2024-04-04 21:04:09 -07:00
Jordan Justen
50c7d25a9e intel/dev/mesa_defs.json: Add LNL WA entries 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28480>
 2024-04-04 21:03:51 -07:00
Jesse Natalie
c891a384e7 dzn: Don't copy app indirect args if we don't need to 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28383>
 2024-04-05 00:25:41 +00:00
Jesse Natalie
db16dcf0f9 dzn: Add a hash table of command signatures with non-default strides 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28383>
 2024-04-05 00:25:41 +00:00
Jesse Natalie
d7bd87aa27 dzn: Rework indirect drawing keys for shaders and command signatures 
When we don't need emulation of first vertex, base instance, draw ID
sysvals, or triangle fans, we can have very simple command signatures
and indirect arg buffer generation shaders. The next step is to handle
the case where everything can be supported straight from the app's
buffer.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28383>
 2024-04-05 00:25:41 +00:00
Jesse Natalie
ccf439629f dzn: Update pipeline cache params to take all options into account 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28383>
 2024-04-05 00:25:41 +00:00
Jesse Natalie
4de88025cc dzn: Understand whether first-vertex and base-instance are needed for a pipeline 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28383>
 2024-04-05 00:25:41 +00:00
Jesse Natalie
fbd4e5d8aa dzn: Query options21 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28383>
 2024-04-05 00:25:41 +00:00
Jesse Natalie
ed465bf738 dzn: Delete dzn structs for indirect draw args and use D3D ones 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28383>
 2024-04-05 00:25:41 +00:00
Jesse Natalie
f6c3d73700 spirv2dxil: Output more specific metadata for whether draw sysvals are needed 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28383>
 2024-04-05 00:25:41 +00:00
Jesse Natalie
30b1a6750c spirv2dxil: Support passing first vertex / base instance to DXIL backend 
These values now have 3 modes of operation so switch from a bool to an enum:
1. Zero
2. Native DXIL sysvals
3. "Runtime data" via a constant buffer or root constants

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28383>
 2024-04-05 00:25:41 +00:00
Jesse Natalie
607720151f microsoft/compiler: Handle base vertex/instance sysvals as DXIL intrinsics 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28383>
 2024-04-05 00:25:41 +00:00
Jesse Natalie
349c4d84c0 ci/windows: Bump Agility SDK to 1.613.2 for ExecuteIndirect validation fix 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28383>
 2024-04-05 00:25:41 +00:00
Ian Romanick
0b67d3d909 intel/elk: Delete stray nir_opt_dce 
No shader-db changes on any Intel platform.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28136>
 2024-04-04 23:42:28 +00:00
Ian Romanick
24cdbbdaa2 intel/brw: Delete stray nir_opt_dce 
No shader-db or fossil-db changes on any Intel platform.

Fixes: f76f4be301 ("intel/compiler: move gen5 final pass to actually be final pass")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28136>
 2024-04-04 23:42:27 +00:00
Ian Romanick
44fb57b827 intel/elk: Don't call nir_opt_remove_phis before nir_convert_from_ssa 
shader-db:

All platforms had similar results. (Ivy Bridge shown)
total instructions in shared programs: 15831424 -> 15831637 (<.01%)
instructions in affected programs: 38880 -> 39093 (0.55%)
helped: 0 / HURT: 179

total cycles in shared programs: 432140353 -> 432170199 (<.01%)
cycles in affected programs: 11798080 -> 11827926 (0.25%)
helped: 77 / HURT: 123

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28136>
 2024-04-04 23:42:27 +00:00
Ian Romanick
6377e8fd29 intel/brw: Don't call nir_opt_remove_phis before nir_convert_from_ssa 
Per discussion in #10727, removing phis breaks LCSSA form which in turn
invalidates divergence analysis.

shader-db:

All Skylake and newer platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 20299612 -> 20299695 (<.01%)
instructions in affected programs: 20829 -> 20912 (0.40%)
helped: 6 / HURT: 13

total cycles in shared programs: 842149085 -> 842148399 (<.01%)
cycles in affected programs: 15146222 -> 15145536 (<.01%)
helped: 40 / HURT: 45

fossil-db:

All Intel platforms had similar results. (Ice Lake shown)
Totals:
Instrs: 165505077 -> 165505603 (+0.00%); split: -0.00%, +0.00%
Cycles: 15144183575 -> 15144235695 (+0.00%); split: -0.00%, +0.00%
Spill count: 45213 -> 45220 (+0.02%)
Fill count: 74166 -> 74184 (+0.02%)

Totals from 94 (0.01% of 656116) affected shaders:
Instrs: 263079 -> 263605 (+0.20%); split: -0.00%, +0.20%
Cycles: 28411487 -> 28463607 (+0.18%); split: -0.18%, +0.37%
Spill count: 3474 -> 3481 (+0.20%)
Fill count: 6713 -> 6731 (+0.27%)

Fixes: 6dbb5f1e07 ("intel/fs: rerun divergence analysis prior to convert_from_ssa")
Closes: #10727
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28136>
 2024-04-04 23:42:27 +00:00
Ian Romanick
87101e7d83 intel/compiler: Ensure load_barycentric_at_sample and load_interpolated_input remain together 
This previously worked by luck because we were incorrectly calling
nir_opt_remove_phis before calling nir_convert_from_ssa. See also #10727.

No shader-db or fossil-db changes on any Intel platform.

v2: Handle the load_interpolated_input and load_barycentric_at_sample as
separate passes. Based on discussion with Ken starting at
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28136#note_2330424.

Fixes: 74a40cc4b6 ("intel/fs: move lower of non-uniform at_sample barycentric to NIR")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28136>
 2024-04-04 23:42:27 +00:00
Erico Nunes
49217c2547 ci: enable shader-db on lima 
Run shader-db on CI with the lima drm_shim as done for other drivers.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24357>
 2024-04-04 22:48:10 +00:00
Samuel Pitoiset
69b911bc53 radv: remove radv_private.h 
This file was a giant mess and I'm very happy to remove it entirely.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28568>
 2024-04-04 21:57:46 +00:00
Samuel Pitoiset
367cf70a29 radv: move RADV_USE_WSI_PLATFORM define to radv_wsi.h 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28568>
 2024-04-04 21:57:46 +00:00
Samuel Pitoiset
28eefbadeb radv: move CLOCK_MONOTONIC_RAW define to radv_physical_device.h 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28568>
 2024-04-04 21:57:46 +00:00
Samuel Pitoiset
e8269c01cb radv: move RADV_API_VERSION to radv_instance.h 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28568>
 2024-04-04 21:57:46 +00:00
Samuel Pitoiset
e25882352b radv: move RADV_SUPPORT_CALIBRATED_TIMESTAMPS to radv_physical_device.c 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28568>
 2024-04-04 21:57:46 +00:00
Samuel Pitoiset
cc1526eeac radv: replace radv_is_aligned() by util_is_aligned() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28568>
 2024-04-04 21:57:46 +00:00
Samuel Pitoiset
81e3c46d06 util: add util_is_aligned() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28568>
 2024-04-04 21:57:46 +00:00
Samuel Pitoiset
5cc3258533 radv: replace radv_float_to_{u,s}fixed() by util_{un}signed_fixed() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28568>
 2024-04-04 21:57:46 +00:00
Samuel Pitoiset
6a27c5e9a8 radv: replace align_u32_npot() by ALIGN_NPOT 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28568>
 2024-04-04 21:57:45 +00:00
Samuel Pitoiset
e75fdac533 radv: replace align_{u32,u64}() by align{64}() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28568>
 2024-04-04 21:57:45 +00:00
Samuel Pitoiset
ba153fc06b radv: replace radv_minify() by u_minify() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28568>
 2024-04-04 21:57:45 +00:00
Samuel Pitoiset
799e99fe21 radv: rename remaining phys_dev occurrences to pdev 
Missed those.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28568>
 2024-04-04 21:57:45 +00:00
Samuel Pitoiset
b409936e97 radv: add missing endif comment for some headers 
For consistency.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28568>
 2024-04-04 21:57:45 +00:00
Samuel Pitoiset
0388df3d08 radv: replace RADV_FROM_HANDLE by VK_FROM_HANDLE 
It was exactly the same thing.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28568>
 2024-04-04 21:57:45 +00:00
Samuel Pitoiset
67ac6e75c6 radv: remove remaining forward declarations and comments in radv_private.h 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28568>
 2024-04-04 21:57:45 +00:00
Samuel Pitoiset
8ade8f28a8 radv: remove pre-declarations needed for WSI entrypoints 
Probably a very old thing.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28568>
 2024-04-04 21:57:45 +00:00
Samuel Pitoiset
46515292a3 radv: remove unused radv_printflike() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28568>
 2024-04-04 21:57:45 +00:00
Jesse Natalie
05b66efb43 d3d12: Add a debug flag for loading WinPixGpuCapturer.dll 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28476>
 2024-04-04 21:37:41 +00:00
Jesse Natalie
116d0bf76b d3d12: Set fractional var masks 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28535>
 2024-04-04 20:29:11 +00:00
Jesse Natalie
c21355260b microsoft/compiler: Add a fractional var mask for variable sorting 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28535>
 2024-04-04 20:29:11 +00:00
Jesse Natalie
760effefc6 d3d12: Don't compile useless variants during shader creation 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28535>
 2024-04-04 20:29:11 +00:00
Jesse Natalie
6928686df9 d3d12: Remove variables instead of adding them for linking 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28535>
 2024-04-04 20:29:11 +00:00
Jesse Natalie
dedbd6eea3 d3d12: Gather info less and before the final compilation steps 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28535>
 2024-04-04 20:29:11 +00:00
Jesse Natalie
c1e7d0598d d3d12: Add primitive ID sysval to input bitmask (for GS in) 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28535>
 2024-04-04 20:29:11 +00:00
Jesse Natalie
c8d435373e d3d12: Use TES inputs rather than VS outputs for TCS variant key 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28535>
 2024-04-04 20:29:11 +00:00
Jesse Natalie
580f801bac d3d12: Capture always_active_io in varying data 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28535>
 2024-04-04 20:29:11 +00:00
Jesse Natalie
5d0c77658c d3d12: Forward front-facing for passthrough GS 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28535>
 2024-04-04 20:29:11 +00:00
Jesse Natalie
d28a552e2a d3d12: Explicitly add tess factor vars to tess signatures 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28535>
 2024-04-04 20:29:11 +00:00