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183087 commits

Author SHA1 Message Date
Samuel Pitoiset
034014a165 aco: restore m0/exec before exiting the trap handler 
Dumping VGPRs will overwrite m0 and exec and they need to be restored
if we want to return to the shader.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32090>
 2024-11-13 15:27:53 +00:00
Samuel Pitoiset
185a165a85 aco: fix validation for v_movrels_b32 and friends 
m0 is the second operand.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32090>
 2024-11-13 15:27:53 +00:00
Samuel Pitoiset
40b343bbee aco: add a new variant for vop1() with two operands 
For v_movrels_b32 and friends which need a second operand for m0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32090>
 2024-11-13 15:27:53 +00:00
Samuel Pitoiset
f4cf6a71ed aco: use a 64-bit mov to save exec in the trap handler shader 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32090>
 2024-11-13 15:27:53 +00:00
Rhys Perry
7d4cc04156 radv,ac/nir: split global access using nir_lower_mem_access_bit_sizes 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31904>
 2024-11-13 12:59:26 +00:00
Rhys Perry
17cc8a5a54 aco: remove load byte_align 
8/16-bit loads given to instruction selection now always use VMEM and
scalar load instructions unless alignment easily allows a vector load.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31904>
 2024-11-13 12:59:26 +00:00
Rhys Perry
8fdc5d7f9f radv,ac/nir: lower sub-dword loads using nir_lower_mem_access_bit_sizes 
fossil-db (navi21):
Totals from 427 (0.54% of 79395) affected shaders:
Instrs: 2939637 -> 2937224 (-0.08%); split: -0.08%, +0.00%
CodeSize: 15982272 -> 15969880 (-0.08%); split: -0.08%, +0.00%
Latency: 21128645 -> 21125738 (-0.01%); split: -0.04%, +0.03%
InvThroughput: 5626811 -> 5626220 (-0.01%); split: -0.03%, +0.02%
SClause: 65771 -> 65731 (-0.06%); split: -0.07%, +0.00%
Copies: 243247 -> 242917 (-0.14%); split: -0.14%, +0.01%
Branches: 100089 -> 100085 (-0.00%)
PreSGPRs: 17879 -> 18118 (+1.34%)
VALU: 1899641 -> 1899278 (-0.02%)
SALU: 468508 -> 466469 (-0.44%)
SMEM: 84305 -> 84291 (-0.02%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31904>
 2024-11-13 12:59:26 +00:00
Rhys Perry
d3ae1842a2 aco,ac/nir: flag loads to use smem in NIR 
This pass will be re-used later.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31904>
 2024-11-13 12:59:26 +00:00
Rhys Perry
7fe4f4c14c nir_lower_mem_access_bit_sizes: support load_constant 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31904>
 2024-11-13 12:59:26 +00:00
Rhys Perry
45c1280d2c nir_lower_mem_access_bit_sizes: pass access to callback 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31904>
 2024-11-13 12:59:26 +00:00
Rhys Perry
61752152f7 nir_lower_mem_access_bit_sizes: add nir_mem_access_shift_method 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31904>
 2024-11-13 12:59:26 +00:00
Rhys Perry
e2dd36c66e nir_lower_mem_access_bit_sizes: support 64-bit offsets 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31904>
 2024-11-13 12:59:26 +00:00
Rhys Perry
0619e4db63 nir,aco,ac/llvm: add nir_op_alignbyte_amd 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31904>
 2024-11-13 12:59:26 +00:00
Rhys Perry
db0cbb7e9b aco: optimize nir_op_shfr with <32 src1 
No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31904>
 2024-11-13 12:59:26 +00:00
Rhys Perry
bd88c8733a ac/nir: add ACCESS_CAN_REORDER to lowered load_global_constant 
fossil-db (navi21):
Totals from 39 (0.05% of 79395) affected shaders:
Instrs: 2619146 -> 2619273 (+0.00%); split: -0.00%, +0.01%
CodeSize: 14158064 -> 14158304 (+0.00%)
Latency: 17277051 -> 17274098 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 4242241 -> 4241746 (-0.01%); split: -0.01%, +0.00%
SClause: 56514 -> 57561 (+1.85%); split: -0.02%, +1.87%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31904>
 2024-11-13 12:59:26 +00:00
Rhys Perry
0c7830eb85 nir/algebraic: optimize ushr(a, ishl(iand(b, 3), 3)) 
nir_lower_mem_access_bit_sizes creates this.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31904>
 2024-11-13 12:59:26 +00:00
Rhys Perry
e95a3364b8 nir/algebraic: optimize bcsel(ieq(b, 0), a, shift(a, b)) 
nir_lower_mem_access_bit_sizes can create this.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31904>
 2024-11-13 12:59:26 +00:00
Rhys Perry
80b76ba692 nir: add more intrinsics to nir_intrinsic_can_reorder 
Including nir_intrinsic_load_global.

fossil-db (navi21):
Totals from 2725 (3.43% of 79395) affected shaders:
MaxWaves: 71972 -> 71964 (-0.01%); split: +0.01%, -0.02%
Instrs: 2831052 -> 2819902 (-0.39%); split: -0.45%, +0.06%
CodeSize: 15047548 -> 14973072 (-0.49%); split: -0.57%, +0.08%
VGPRs: 108864 -> 108856 (-0.01%); split: -0.02%, +0.01%
SpillSGPRs: 906 -> 926 (+2.21%)
SpillVGPRs: 196 -> 1092 (+457.14%)
Scratch: 729088 -> 741376 (+1.69%)
Latency: 16621317 -> 16586551 (-0.21%); split: -0.34%, +0.13%
InvThroughput: 4169987 -> 4164876 (-0.12%); split: -0.23%, +0.11%
VClause: 63247 -> 63471 (+0.35%); split: -0.21%, +0.56%
SClause: 56978 -> 55276 (-2.99%); split: -3.50%, +0.51%
Copies: 252545 -> 252495 (-0.02%); split: -0.98%, +0.96%
Branches: 91378 -> 91388 (+0.01%); split: -0.03%, +0.04%
PreSGPRs: 112753 -> 126850 (+12.50%); split: -0.48%, +12.98%
PreVGPRs: 90617 -> 90708 (+0.10%)
VALU: 1709034 -> 1709368 (+0.02%); split: -0.01%, +0.03%
SALU: 463554 -> 462253 (-0.28%); split: -0.57%, +0.29%
VMEM: 115952 -> 116272 (+0.28%); split: -0.21%, +0.49%
SMEM: 129097 -> 120538 (-6.63%); split: -6.64%, +0.01%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31904>
 2024-11-13 12:59:26 +00:00
Eric Engestrom
c925730779 freedreno/ci: document flakes seen recently 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32080>
 2024-11-13 12:26:50 +00:00
Eric Engestrom
234b9c72f9 nvk/ci: document flakes seen recently 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32080>
 2024-11-13 12:26:50 +00:00
Eric Engestrom
d688a25d7e broadcom/ci: document flakes seen recently 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32080>
 2024-11-13 12:26:50 +00:00
Eric Engestrom
6018d15f32 radv/ci: document flakes seen recently 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32080>
 2024-11-13 12:26:49 +00:00
Samuel Pitoiset
0c77469995 aco: fix saving/restoring VGPRS in the trap handler on GFX9 
When ADD_TID_ENABLE=1, DATA_FORMAT is STRIDE[14:17], so the stride
was too large.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32109>
 2024-11-13 11:12:54 +00:00
Erik Faye-Lund
62da644221 panfrost: use mesa_log infra instead of stdio 
It's generally useful to use mesa_log for error messages etc. This makes
it easier to forward diagnostics into the right logs etc.

So let's be more consistent about where we're logging things.

Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32094>
 2024-11-13 09:15:05 +00:00
Erik Faye-Lund
c53b944453 panvk: drop unused include 
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32094>
 2024-11-13 09:15:05 +00:00
Tomeu Vizoso
936da3eb9c etnaviv/ml: Zero out the NN config 
As some bits were being left unitialized and causing flakiness.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31842>
 2024-11-13 07:39:35 +00:00
Tomeu Vizoso
b3057ab511 etnaviv/ci: Update expectations for the NPU in the A311D 
Several tests have been fixed with the changes to enable the NPU in the
i.MX8MP.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31842>
 2024-11-13 07:39:35 +00:00
Tomeu Vizoso
459da82db6 etnaviv/ml: Make use of the new depthwise support in V8 
The V8 hardware supports a faster way of executing depthwise
convolutions, instead of having to fully lower them to regular
convolutions.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31842>
 2024-11-13 07:39:35 +00:00
Tomeu Vizoso
63a10f770c etnaviv/ml: Only reshuffle when needed on V8 
Because of how depthwise convolutions are implemented on V8, we
sometimes don't need reshuffling the input with strided convolutions.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31842>
 2024-11-13 07:39:35 +00:00
Tomeu Vizoso
93298a873b etnaviv/ml: Fix reshuffle TP jobs on V8 
What we had didn't work on V8, but with these fixes for V8, these jobs
still run well on V7.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31842>
 2024-11-13 07:39:35 +00:00
Tomeu Vizoso
f186844545 etnaviv/ml: Disable caching on V8 
The assumptions we make on V7 doesnt work as-is on V8.

Revisit this later.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31842>
 2024-11-13 07:39:35 +00:00
Tomeu Vizoso
41a9540ab9 etnaviv/ml: Set two bits in the NN instruction for V8 
Not sure why they have to be set, but they are always on V8.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31842>
 2024-11-13 07:39:35 +00:00
Tomeu Vizoso
bb06e082f8 etnaviv/ml: Implement tiling for V8 
Have had to tweak the code to stay safe on the i.MX8MP.

Also, we are for now being very conservative with tiling to prevent
underruns.

In the future, we may want to consider testing different possibilities
during compilation and choosing the optimal one. Also maybe detecting
underruns by checking whether the NPU hung with a given combination.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31842>
 2024-11-13 07:39:35 +00:00
Tomeu Vizoso
0ef5aa5fb6 etnaviv/ml: Fix padding for convolutions in V8 
Two bits that aren't used in V7 seem to be used for this in V8.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31842>
 2024-11-13 07:39:35 +00:00
Tomeu Vizoso
b4ba62fcda etnaviv/ml: Add encoding of coefficients for V8 
In V8 the weights and biases of convolution operations are encoded with
a totally different scheme.

The initial reverse engineering and implementation was done by:

Philipp Zabel <p.zabel@pengutronix.de>

Support for zero run length encoding and average bias is not implemented yet.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31842>
 2024-11-13 07:39:35 +00:00
Tomeu Vizoso
f3d765ed5d etnaviv/ml: Split V7 coefficient encoding to a new file 
In preparation for V8 support, which uses a completely different
encoding.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31842>
 2024-11-13 07:39:35 +00:00
Tomeu Vizoso
3744defc7e etnaviv: Add script to decode weights in Huffman format 
The bitstream encoding is based on information reverse engineered by:

Philipp Zabel <p.zabel@pengutronix.de>

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31842>
 2024-11-13 07:39:35 +00:00
Tomeu Vizoso
88b5b998d2 etnaviv/ml: Rework the dumping of tensors 
Name the file dumps after the operation and suboperation they belong to.

Also dump the command stream for each operation.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31842>
 2024-11-13 07:39:35 +00:00
Tomeu Vizoso
4ca98fa662 etnaviv/ci: Add expectation files for the VIPNano-SI+ NPU 
This is the NPU in the NXP i.MX8MP SoC.

Initially, only convolutions are supported.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31842>
 2024-11-13 07:39:35 +00:00
Tomeu Vizoso
f9bb9aa7d5 etnaviv/nn: Fix use of etna_core_info 
Right now we were retrieving the properties of the NPU from the
etna_core_info of the GPU.

Fixes: 92a6f697d5 ("etnaviv: npu: Switch to use etna_core_info")
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31842>
 2024-11-13 07:39:35 +00:00
Tomeu Vizoso
70bff0c971 etnaviv/ml: Fix includes 
etnaviv_ml.h uses dynarray, but the u_inlines.h header is needed by
some of the files that include it.

Fixes: d6473ce28e ("etnaviv: Use NN cores to accelerate convolutions")
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31842>
 2024-11-13 07:39:35 +00:00
Peyton Lee
79b34a6539 frontends/va: add support for VAProcColorStandardExplicit 
for video post processing,
add support for VAProcColorStandardExplicit

Signed-off-by: Peyton Lee <peytolee@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32087>
 2024-11-13 06:52:39 +00:00
Peyton Lee
a9e4461c26 frontends/va: add support for VAProcColorStandardExplicit 
for video post processing,
add support for VAProcColorStandardExplicit

Signed-off-by: Peyton Lee <peytolee@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32087>
 2024-11-13 06:52:39 +00:00
Tapani Pälli
fbe5d41b58 anv: extend Wa_14017794102 with lineage Wa_14023061436 
This workaround is applicable for Xe3 with new lineage.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31963>
 2024-11-13 04:54:32 +00:00
Tapani Pälli
9429c0075b anv: utilize ray query bo per queue for Wa_14022863161 
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31963>
 2024-11-13 04:54:32 +00:00
Tapani Pälli
1bd9e51a73 intel/dev: update mesa_defs.json from workaround database 
Brings in some PTL workarounds.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31963>
 2024-11-13 04:54:32 +00:00
Benjamin Otte
e757238370 vulkan/wsi: Support alpha swapchains on win32 
Map VkSwapchainCreateInfoKHR.compositeAlpha to corresponding
DXGI_SWAP_CHAIN_DESC1.alphaMode.

Add VK_COMPOSITE_ALPHA_POST_MULTIPLIED_BIT_KHR to capabilities as
it was missing there.

Signed-off-by: Benjamin Otte <otte@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32048>
 2024-11-13 04:26:46 +00:00
Iván Briano
f2f4206d49 intel/decoder: fix INTEL_DEBUG=bat 
Now that all genxml filenames are in verx10 format, we don't need to fix
the number up when we look them up.

Fixes: 8906816f49 ("anv,hasvk,genxml: Rename genxml files using verx10")

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32099>
 2024-11-13 00:45:40 +00:00
M Henning
68cdcf5bbc nvk: Fix two typos in comments 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32086>
 2024-11-12 23:26:49 +00:00
M Henning
05770374a3 nvk: Remove params for dirty_cbufs_for_descriptors 
dyn_start/dyn_end are unused now.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32086>
 2024-11-12 23:26:49 +00:00