fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-21 11:30:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

tu, freedreno: Write PC_DGEN_SU_CONSERVATIVE_RAS_CNTL

Browse source 
Prevent other processes writing this from messing us up.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33152>
This commit is contained in:
Connor Abbott 2025-01-21 16:35:11 -05:00 • committed by Marge Bot
parent 6701806cd1
commit ffe8220bbd
2 changed files with 4 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/freedreno/vulkan/tu_cmd_buffer.cc
View file

@ -1483,6 +1483,8 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
tu_cs_emit_regs(cs, A7XX_PC_TESS_FACTOR_SIZE(TU_TESS_FACTOR_SIZE));
}
tu_cs_emit_regs(cs, A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL());
/* There is an optimization to skip executing draw states for draws with no
* instances. Instead of simply skipping the draw, internally the firmware
* sets a bit in PC_DRAW_INITIATOR that seemingly skips the draw. However

2
src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
View file

@ -1038,6 +1038,8 @@ fd6_emit_static_regs(struct fd_context *ctx, struct fd_ringbuffer *ring)
OUT_PKT4(ring, REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR, 2);
OUT_RELOC(ring, bcolor_mem, 0, 0, 0);
OUT_REG(ring, A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL());
/* These regs are blocked (CP_PROTECT) on a6xx: */
if (CHIP >= A7XX) {
OUT_REG(ring,