From ffe8220bbdced8105d68d6dafecab7a38345b08c Mon Sep 17 00:00:00 2001 From: Connor Abbott Date: Tue, 21 Jan 2025 16:35:11 -0500 Subject: [PATCH] tu, freedreno: Write PC_DGEN_SU_CONSERVATIVE_RAS_CNTL Prevent other processes writing this from messing us up. Cc: mesa-stable Part-of: --- src/freedreno/vulkan/tu_cmd_buffer.cc | 2 ++ src/gallium/drivers/freedreno/a6xx/fd6_emit.cc | 2 ++ 2 files changed, 4 insertions(+) diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc index 737ddba1d46..81cfa3cc792 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.cc +++ b/src/freedreno/vulkan/tu_cmd_buffer.cc @@ -1483,6 +1483,8 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs) tu_cs_emit_regs(cs, A7XX_PC_TESS_FACTOR_SIZE(TU_TESS_FACTOR_SIZE)); } + tu_cs_emit_regs(cs, A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL()); + /* There is an optimization to skip executing draw states for draws with no * instances. Instead of simply skipping the draw, internally the firmware * sets a bit in PC_DRAW_INITIATOR that seemingly skips the draw. However diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc b/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc index 9326503cb0c..89ed01437d4 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc @@ -1038,6 +1038,8 @@ fd6_emit_static_regs(struct fd_context *ctx, struct fd_ringbuffer *ring) OUT_PKT4(ring, REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR, 2); OUT_RELOC(ring, bcolor_mem, 0, 0, 0); + OUT_REG(ring, A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL()); + /* These regs are blocked (CP_PROTECT) on a6xx: */ if (CHIP >= A7XX) { OUT_REG(ring,