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freedreno/decode: Improved reg64 decoding

Browse source 
This also (other than for an a5xx hack) gets rid of relying on
type0_reg_vals which isn't updated in all paths.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20456>
This commit is contained in:
Rob Clark 2022-12-29 11:39:05 -08:00 • committed by Marge Bot
parent 59f2748163
commit ffb77c8be6
8 changed files with 337 additions and 571 deletions
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575
src/freedreno/.gitlab-ci/reference/crash.log
View file

File diff suppressed because it is too large Load diff

38
src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
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@ -207,23 +207,18 @@ cmdstream[0]: 265 dwords
0000000001058214: 0000: 40889801 00000000
write SP_TP_BORDER_COLOR_BASE_ADDR (b302)
SP_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0
000000000105821c: 0000: 48b30202 01011000 00000000
write SP_PS_TP_BORDER_COLOR_BASE_ADDR (b180)
SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
SP_PS_TP_BORDER_COLOR_BASE_ADDR_HI: 0
0000000001058228: 0000: 40b18002 01011000 00000000
write VSC_DRAW_STRM_SIZE_ADDRESS (0c03)
VSC_DRAW_STRM_SIZE_ADDRESS: 0x10fd000
VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0
0000000001058234: 0000: 480c0302 010fd000 00000000
write VSC_PRIM_STRM_ADDRESS (0c30)
VSC_PRIM_STRM_ADDRESS: 0x105c000
VSC_PRIM_STRM_ADDRESS_HI: 0
0000000001058240: 0000: 480c3002 0105c000 00000000
write VSC_DRAW_STRM_ADDRESS (0c34)
VSC_DRAW_STRM_ADDRESS: 0x10dc800
VSC_DRAW_STRM_ADDRESS_HI: 0
000000000105824c: 0000: 400c3402 010dc800 00000000
opcode: CP_EVENT_WRITE (46) (5 dwords)
{ EVENT = PC_CCU_FLUSH_COLOR_TS }
@ -263,12 +258,10 @@ cmdstream[0]: 265 dwords
write RB_2D_DST_INFO (8c17)
RB_2D_DST_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX | FLAGS | SAMPLES = MSAA_ONE }
RB_2D_DST: 0x1013000
RB_2D_DST_HI: 0
RB_2D_DST_PITCH: 1024
00000000010582b8: 0000: 408c1704 00001330 01013000 00000000 00000010
write RB_2D_DST_FLAGS (8c20)
RB_2D_DST_FLAGS: 0x1012000
RB_2D_DST_FLAGS_HI: 0
RB_2D_DST_FLAGS_PITCH: 64 | 0x4000
00000000010582cc: 0000: 488c2083 01012000 00000000 00004001
opcode: CP_BLIT (2c) (2 dwords)
@ -277,11 +270,8 @@ cmdstream[0]: 265 dwords
skip_ib2: g=0, l=0
draw[0] register values
!+ 010fd000 VSC_DRAW_STRM_SIZE_ADDRESS: 0x10fd000
+ 00000000 VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0
!+ 0105c000 VSC_PRIM_STRM_ADDRESS: 0x105c000
+ 00000000 VSC_PRIM_STRM_ADDRESS_HI: 0
!+ 010dc800 VSC_DRAW_STRM_ADDRESS: 0x10dc800
+ 00000000 VSC_DRAW_STRM_ADDRESS_HI: 0
!+ 03200000 UCHE_UNKNOWN_0E12: 0x3200000
!+ 00000004 UCHE_CLIENT_PF: { PERFSEL = 0x4 }
+ 00000000 GRAS_SU_CONSERVATIVE_RAS_CNTL: { SHIFTAMOUNT = 0 }
@ -311,10 +301,8 @@ cmdstream[0]: 265 dwords
+ 00000000 RB_2D_UNKNOWN_8C01: 0
!+ 00001330 RB_2D_DST_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX | FLAGS | SAMPLES = MSAA_ONE }
!+ 01013000 RB_2D_DST: 0x1013000
+ 00000000 RB_2D_DST_HI: 0
!+ 00000010 RB_2D_DST_PITCH: 1024
!+ 01012000 RB_2D_DST_FLAGS: 0x1012000
+ 00000000 RB_2D_DST_FLAGS_HI: 0
!+ 00004001 RB_2D_DST_FLAGS_PITCH: 64 | 0x4000
+ 00000000 RB_2D_SRC_SOLID_C0: 0
+ 00000000 RB_2D_SRC_SOLID_C1: 0
@ -352,11 +340,9 @@ cmdstream[0]: 265 dwords
!+ 00000008 SP_FLOAT_CNTL: { F16_NO_INF }
!+ 0000003f SP_PERFCTR_ENABLE: { VS | HS | DS | GS | FS | CS }
!+ 01011000 SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
+ 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR_HI: 0
+ 00000000 SP_UNKNOWN_B182: 0
+ 00000000 SP_UNKNOWN_B183: 0
!+ 01011000 SP_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
+ 00000000 SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0
!+ 000000a2 SP_TP_MODE_CNTL: { ISAMMODE = ISAMMODE_GL | UNK3 = 0x28 }
!+ 00100000 TPL1_DBG_ECO_CNTL: 0x100000
!+ 00000044 TPL1_UNKNOWN_B605: 68
@ -465,12 +451,10 @@ cmdstream[0]: 265 dwords
write RB_BLIT_DST_INFO (88d7)
RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
RB_BLIT_DST: 0x1013000
RB_BLIT_DST_HI: 0
RB_BLIT_DST_PITCH: 1024
000000000115e028: 0000: 4888d704 00001807 01013000 00000000 00000010
write RB_BLIT_FLAG_DST (88dc)
RB_BLIT_FLAG_DST: 0x1012000
RB_BLIT_FLAG_DST_HI: 0
RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
000000000115e03c: 0000: 4088dc83 01012000 00000000 00004001
write RB_BLIT_BASE_GMEM (88d6)
@ -497,10 +481,8 @@ cmdstream[0]: 265 dwords
+ 00000000 RB_BLIT_BASE_GMEM: 0
!+ 00001807 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
!+ 01013000 RB_BLIT_DST: 0x1013000
+ 00000000 RB_BLIT_DST_HI: 0
!+ 00000010 RB_BLIT_DST_PITCH: 1024
!+ 01012000 RB_BLIT_FLAG_DST: 0x1012000
+ 00000000 RB_BLIT_FLAG_DST_HI: 0
!+ 00004001 RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
!+ 00000003 RB_BLIT_INFO: { UNK0 | GMEM | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
!+ 7c400000 RB_CCU_CNTL: { COLOR_OFFSET = 0xf8000 | DEPTH_OFFSET = 0 | GMEM }
@ -521,7 +503,6 @@ cmdstream[0]: 265 dwords
RB_DEPTH_BUFFER_PITCH: 0
RB_DEPTH_BUFFER_ARRAY_PITCH: 0
RB_DEPTH_BUFFER_BASE: 0
RB_DEPTH_BUFFER_BASE_HI: 0
RB_DEPTH_BUFFER_BASE_GMEM: 0
000000000115e074: 0000: 48887286 00000000 00000000 00000000 00000000 00000000 00000000
write GRAS_SU_DEPTH_BUFFER_INFO (8098)
@ -529,10 +510,8 @@ cmdstream[0]: 265 dwords
000000000115e090: 0000: 48809801 00000000
write GRAS_LRZ_BUFFER_BASE (8103)
GRAS_LRZ_BUFFER_BASE: 0
GRAS_LRZ_BUFFER_BASE_HI: 0
GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0
GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
000000000115e098: 0000: 48810385 00000000 00000000 00000000 00000000 00000000
write RB_STENCIL_INFO (8881)
RB_STENCIL_INFO: { 0 }
@ -542,7 +521,6 @@ cmdstream[0]: 265 dwords
RB_MRT[0].PITCH: 1024
RB_MRT[0].ARRAY_PITCH: 262144
RB_MRT[0].BASE: 0x1013000
RB_MRT[0].BASE_HI: 0
RB_MRT[0].BASE_GMEM: 0
000000000115e0b8: 0000: 48882286 00000330 00000010 00001000 01013000 00000000 00000000
write SP_FS_MRT[0].REG (a996)
@ -550,7 +528,6 @@ cmdstream[0]: 265 dwords
000000000115e0d4: 0000: 48a99601 00000030
write RB_MRT_FLAG_BUFFER[0].ADDR (8903)
RB_MRT_FLAG_BUFFER[0].ADDR: 0x1012000
RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
000000000115e0dc: 0000: 40890383 01012000 00000000 00004001
write RB_SRGB_CNTL (880f)
@ -814,7 +791,6 @@ cmdstream[0]: 265 dwords
- shaderdb: 0 last-baryf, 0 half, 3 full, 2 constlen
- shaderdb: 8 cat0, 0 cat1, 1 cat2, 4 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
SP_VS_OBJ_START_HI: 0
00000000010541a4: 0000: 48a81c02 01054000 00000000
opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 }
@ -892,7 +868,6 @@ cmdstream[0]: 265 dwords
- shaderdb: 3 last-baryf, 0 half, 2 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
SP_FS_OBJ_START_HI: 0
000000000105422c: 0000: 40a98302 01054080 00000000
opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords)
{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_FS_SHADER | NUM_UNIT = 1 }
@ -1070,7 +1045,6 @@ cmdstream[0]: 265 dwords
000000000115c070: 0000: 40a01083 01053000 00000000 00000318
write VFD_FETCH[0].BASE (a010)
VFD_FETCH[0].BASE: 0x1053000
VFD_FETCH[0].BASE_HI: 0
VFD_FETCH[0].SIZE: 792
000000000115c070: 0000: 40a01083 01053000 00000000 00000318
group_id: 4
@ -1341,10 +1315,8 @@ cmdstream[0]: 265 dwords
!+ 00ff00ff GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 255 | Y = 255 }
+ 00000000 GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
+ 00000000 GRAS_LRZ_BUFFER_BASE: 0
+ 00000000 GRAS_LRZ_BUFFER_BASE_HI: 0
+ 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
+ 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0
+ 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
+ 00000000 GRAS_SAMPLE_CNTL: { 0 }
!+ 00010010 RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0x1 }
+ 00000000 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
@ -1363,7 +1335,6 @@ cmdstream[0]: 265 dwords
!+ 00000010 RB_MRT[0].PITCH: 1024
!+ 00001000 RB_MRT[0].ARRAY_PITCH: 262144
!+ 01013000 RB_MRT[0].BASE: 0x1013000
+ 00000000 RB_MRT[0].BASE_HI: 0
+ 00000000 RB_MRT[0].BASE_GMEM: 0
!+ dffe8440 RB_BLEND_RED_F32: -36679707902607360000.000000
!+ 0000ffff RB_BLEND_GREEN_F32: 0.000000
@ -1377,7 +1348,6 @@ cmdstream[0]: 265 dwords
+ 00000000 RB_DEPTH_BUFFER_PITCH: 0
+ 00000000 RB_DEPTH_BUFFER_ARRAY_PITCH: 0
+ 00000000 RB_DEPTH_BUFFER_BASE: 0
+ 00000000 RB_DEPTH_BUFFER_BASE_HI: 0
+ 00000000 RB_DEPTH_BUFFER_BASE_GMEM: 0
+ 00000000 RB_Z_BOUNDS_MIN: 0.000000
+ 00000000 RB_Z_BOUNDS_MAX: 0.000000
@ -1392,7 +1362,6 @@ cmdstream[0]: 265 dwords
+ 00ff00ff RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
+ 00000000 RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
!+ 01012000 RB_MRT_FLAG_BUFFER[0].ADDR: 0x1012000
+ 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
!+ 00004001 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
!+ 00ffff00 VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
!+ 0000ffff VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 }
@ -1434,7 +1403,6 @@ cmdstream[0]: 265 dwords
!+ 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x }
+ 00000000 VFD_CONTROL_6: { 0 }
!+ 01053000 VFD_FETCH[0].BASE: 0x1053000
+ 00000000 VFD_FETCH[0].BASE_HI: 0
!+ 00000318 VFD_FETCH[0].SIZE: 792
!+ 00000024 VFD_FETCH[0].STRIDE: 36
!+ c8200000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT }
@ -1472,7 +1440,6 @@ cmdstream[0]: 265 dwords
- shaderdb: 0 last-baryf, 0 half, 3 full, 2 constlen
- shaderdb: 8 cat0, 0 cat1, 1 cat2, 4 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
+ 00000000 SP_VS_OBJ_START_HI: 0
!+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 00000001 SP_VS_INSTRLEN: 1
+ 00000000 SP_HS_WAVE_INPUT_SIZE: 0
@ -1500,7 +1467,6 @@ cmdstream[0]: 265 dwords
- shaderdb: 3 last-baryf, 0 half, 2 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
+ 00000000 SP_FS_OBJ_START_HI: 0
!+ 00000100 SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 }
+ 00000000 SP_SRGB_CNTL: { 0 }
!+ 0000000f SP_FS_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
@ -1564,12 +1530,10 @@ cmdstream[0]: 265 dwords
write RB_BLIT_DST_INFO (88d7)
RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
RB_BLIT_DST: 0x1013000
RB_BLIT_DST_HI: 0
RB_BLIT_DST_PITCH: 1024
000000000115c03c: 0000: 4888d704 00001807 01013000 00000000 00000010
write RB_BLIT_FLAG_DST (88dc)
RB_BLIT_FLAG_DST: 0x1012000
RB_BLIT_FLAG_DST_HI: 0
RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
000000000115c050: 0000: 4088dc83 01012000 00000000 00004001
write RB_BLIT_BASE_GMEM (88d6)
@ -1587,10 +1551,8 @@ cmdstream[0]: 265 dwords
+ 00000000 RB_BLIT_BASE_GMEM: 0
+ 00001807 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
+ 01013000 RB_BLIT_DST: 0x1013000
+ 00000000 RB_BLIT_DST_HI: 0
+ 00000010 RB_BLIT_DST_PITCH: 1024
+ 01012000 RB_BLIT_FLAG_DST: 0x1012000
+ 00000000 RB_BLIT_FLAG_DST_HI: 0
+ 00004001 RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
!+ 00000000 RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
000000000115c068: 0000: 70460001 0000001e

30
src/freedreno/.gitlab-ci/reference/fd-clouds.log
View file

@ -252,7 +252,6 @@ cmdstream[0]: 1023 dwords
RB_DEPTH_BUFFER_PITCH: 0
RB_DEPTH_BUFFER_ARRAY_PITCH: 0
RB_DEPTH_BUFFER_BASE: 0
RB_DEPTH_BUFFER_BASE_HI: 0
RB_DEPTH_BUFFER_BASE_GMEM: 0
0000000001d91284: 0000: 48887286 00000000 00000000 00000000 00000000 00000000 00000000
write GRAS_SU_DEPTH_BUFFER_INFO (8098)
@ -260,10 +259,8 @@ cmdstream[0]: 1023 dwords
0000000001d912a0: 0000: 48809801 00000000
write GRAS_LRZ_BUFFER_BASE (8103)
GRAS_LRZ_BUFFER_BASE: 0
GRAS_LRZ_BUFFER_BASE_HI: 0
GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0
GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
0000000001d912a8: 0000: 48810385 00000000 00000000 00000000 00000000 00000000
write RB_STENCIL_INFO (8881)
RB_STENCIL_INFO: { 0 }
@ -273,7 +270,6 @@ cmdstream[0]: 1023 dwords
RB_MRT[0].PITCH: 8704
RB_MRT[0].ARRAY_PITCH: 12533760
RB_MRT[0].BASE: 0x1125000
RB_MRT[0].BASE_HI: 0
RB_MRT[0].BASE_GMEM: 0
0000000001d912c8: 0000: 48882286 00002031 00000088 0002fd00 01125000 00000000 00000000
write SP_FS_MRT[0].REG (a996)
@ -281,7 +277,6 @@ cmdstream[0]: 1023 dwords
0000000001d912e4: 0000: 48a99601 00000031
write RB_MRT_FLAG_BUFFER[0].ADDR (8903)
RB_MRT_FLAG_BUFFER[0].ADDR: 0
RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
0000000001d912ec: 0000: 40890383 00000000 00000000 00000000
write RB_SRGB_CNTL (880f)
@ -365,7 +360,6 @@ cmdstream[0]: 1023 dwords
write VSC_BIN_SIZE (0c02)
VSC_BIN_SIZE: { WIDTH = 544 | HEIGHT = 480 }
VSC_DRAW_STRM_SIZE_ADDRESS: 0x1d65800
VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0
0000000001d913d4: 0000: 400c0283 00001e11 01d65800 00000000
write VSC_BIN_COUNT (0c06)
VSC_BIN_COUNT: { NX = 4 | NY = 3 }
@ -408,13 +402,11 @@ cmdstream[0]: 1023 dwords
*
write VSC_PRIM_STRM_ADDRESS (0c30)
VSC_PRIM_STRM_ADDRESS: 0x1d67000
VSC_PRIM_STRM_ADDRESS_HI: 0
VSC_PRIM_STRM_PITCH: 0x1040
VSC_PRIM_STRM_LIMIT: 0x28000
0000000001d91470: 0000: 480c3004 01d67000 00000000 00001040 00028000
write VSC_DRAW_STRM_ADDRESS (0c34)
VSC_DRAW_STRM_ADDRESS: 0x1d5d000
VSC_DRAW_STRM_ADDRESS_HI: 0
VSC_DRAW_STRM_PITCH: 0x440
VSC_DRAW_STRM_LIMIT: 0xa000
0000000001d91484: 0000: 400c3404 01d5d000 00000000 00000440 0000a000
@ -637,7 +629,6 @@ cmdstream[0]: 1023 dwords
- shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
SP_VS_OBJ_START_HI: 0
0000000001121038: 0000: 48a81c02 01011000 00000000
opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 }
@ -779,7 +770,6 @@ cmdstream[0]: 1023 dwords
0000000001116020: 0020: 40a0d001 0000000f 48a00001 00000101
write VFD_FETCH[0].BASE (a010)
VFD_FETCH[0].BASE: 0x1016000
VFD_FETCH[0].BASE_HI: 0
VFD_FETCH[0].SIZE: 1048576
VFD_FETCH[0].STRIDE: 12
0000000001116000: 0000: 40a01004 01016000 00000000 00100000 0000000c
@ -875,7 +865,6 @@ cmdstream[0]: 1023 dwords
:0,1,11,2
!+ 00001e11 VSC_BIN_SIZE: { WIDTH = 544 | HEIGHT = 480 }
!+ 01d65800 VSC_DRAW_STRM_SIZE_ADDRESS: 0x1d65800
+ 00000000 VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0
!+ 00001808 VSC_BIN_COUNT: { NX = 4 | NY = 3 }
!+ 04100000 VSC_PIPE_CONFIG[0].REG: { X = 0 | Y = 0 | W = 1 | H = 1 }
!+ 04100001 VSC_PIPE_CONFIG[0x1].REG: { X = 1 | Y = 0 | W = 1 | H = 1 }
@ -910,11 +899,9 @@ cmdstream[0]: 1023 dwords
+ 00000000 VSC_PIPE_CONFIG[0x1e].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
+ 00000000 VSC_PIPE_CONFIG[0x1f].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
!+ 01d67000 VSC_PRIM_STRM_ADDRESS: 0x1d67000
+ 00000000 VSC_PRIM_STRM_ADDRESS_HI: 0
!+ 00001040 VSC_PRIM_STRM_PITCH: 0x1040
!+ 00028000 VSC_PRIM_STRM_LIMIT: 0x28000
!+ 01d5d000 VSC_DRAW_STRM_ADDRESS: 0x1d5d000
+ 00000000 VSC_DRAW_STRM_ADDRESS_HI: 0
!+ 00000440 VSC_DRAW_STRM_PITCH: 0x440
!+ 0000a000 VSC_DRAW_STRM_LIMIT: 0xa000
!+ 03200000 UCHE_UNKNOWN_0E12: 0x3200000
@ -957,10 +944,8 @@ cmdstream[0]: 1023 dwords
+ 00000000 GRAS_LRZ_CNTL: { DIR = 0 }
+ 00000000 GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER }
+ 00000000 GRAS_LRZ_BUFFER_BASE: 0
+ 00000000 GRAS_LRZ_BUFFER_BASE_HI: 0
+ 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
+ 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0
+ 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
+ 00000000 GRAS_SAMPLE_CNTL: { 0 }
!+ 00000002 GRAS_UNKNOWN_8110: 0x2
+ 00000000 GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 }
@ -990,7 +975,6 @@ cmdstream[0]: 1023 dwords
!+ 00000088 RB_MRT[0].PITCH: 8704
!+ 0002fd00 RB_MRT[0].ARRAY_PITCH: 12533760
!+ 01125000 RB_MRT[0].BASE: 0x1125000
+ 00000000 RB_MRT[0].BASE_HI: 0
+ 00000000 RB_MRT[0].BASE_GMEM: 0
+ 00000000 RB_BLEND_RED_F32: 0.000000
+ 00000000 RB_BLEND_GREEN_F32: 0.000000
@ -1004,7 +988,6 @@ cmdstream[0]: 1023 dwords
+ 00000000 RB_DEPTH_BUFFER_PITCH: 0
+ 00000000 RB_DEPTH_BUFFER_ARRAY_PITCH: 0
+ 00000000 RB_DEPTH_BUFFER_BASE: 0
+ 00000000 RB_DEPTH_BUFFER_BASE_HI: 0
+ 00000000 RB_DEPTH_BUFFER_BASE_GMEM: 0
+ 00000000 RB_Z_BOUNDS_MIN: 0.000000
+ 00000000 RB_Z_BOUNDS_MAX: 0.000000
@ -1019,7 +1002,6 @@ cmdstream[0]: 1023 dwords
+ 00000000 RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
+ 00000000 RB_UNKNOWN_88F0: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0].ADDR: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
!+ 00000001 RB_UNKNOWN_8E01: 0x1
+ 00000000 RB_DBG_ECO_CNTL: 0
@ -1068,7 +1050,6 @@ cmdstream[0]: 1023 dwords
+ 00000000 VFD_INDEX_OFFSET: 0
+ 00000000 VFD_INSTANCE_START_OFFSET: 0
!+ 01016000 VFD_FETCH[0].BASE: 0x1016000
+ 00000000 VFD_FETCH[0].BASE_HI: 0
!+ 00100000 VFD_FETCH[0].SIZE: 1048576
!+ 0000000c VFD_FETCH[0].STRIDE: 12
!+ c7400000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT }
@ -1093,7 +1074,6 @@ cmdstream[0]: 1023 dwords
- shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
+ 00000000 SP_VS_OBJ_START_HI: 0
!+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 00000001 SP_VS_INSTRLEN: 1
+ 00000000 SP_HS_WAVE_INPUT_SIZE: 0
@ -1931,7 +1911,6 @@ cmdstream[0]: 1023 dwords
- shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
SP_VS_OBJ_START_HI: 0
0000000001120038: 0000: 48a81c02 01012000 00000000
opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 }
@ -3464,7 +3443,6 @@ cmdstream[0]: 1023 dwords
- shaderdb: 0 last-baryf, 0 half, 19 full, 29 constlen
- shaderdb: 1120 cat0, 48 cat1, 551 cat2, 512 cat3, 183 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 1326 sstall, 140 (ss), 0 (sy)
SP_FS_OBJ_START_HI: 0
0000000001120158: 0000: 40a98302 01013000 00000000
opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords)
{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_FS_SHADER | NUM_UNIT = 88 }
@ -4996,7 +4974,6 @@ cmdstream[0]: 1023 dwords
0000000001116020: 0020: 40a0d001 0000000f 48a00001 00000101
write VFD_FETCH[0].BASE (a010)
VFD_FETCH[0].BASE: 0x1016000
VFD_FETCH[0].BASE_HI: 0
VFD_FETCH[0].SIZE: 1048576
VFD_FETCH[0].STRIDE: 12
0000000001116000: 0000: 40a01004 01016000 00000000 00100000 0000000c
@ -5043,7 +5020,6 @@ cmdstream[0]: 1023 dwords
00000000011160a0: 0000: 70b68003 003a0000 011160a0 00000000
write SP_IBO (ab1a)
SP_IBO: 0x11160a0 base=1116000, offset=160, size=388
SP_IBO_HI: 0
00000000011160b0: 0000: 48ab1a02 011160a0 00000000
write SP_IBO_COUNT (ab20)
SP_IBO_COUNT: 0
@ -5268,7 +5244,6 @@ cmdstream[0]: 1023 dwords
+ 00000000 VFD_INDEX_OFFSET: 0
+ 00000000 VFD_INSTANCE_START_OFFSET: 0
+ 01016000 VFD_FETCH[0].BASE: 0x1016000
+ 00000000 VFD_FETCH[0].BASE_HI: 0
+ 00100000 VFD_FETCH[0].SIZE: 1048576
+ 0000000c VFD_FETCH[0].STRIDE: 12
+ c7400000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT }
@ -5291,7 +5266,6 @@ cmdstream[0]: 1023 dwords
- shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
+ 00000000 SP_VS_OBJ_START_HI: 0
+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000001 SP_VS_INSTRLEN: 1
+ 00000000 SP_HS_WAVE_INPUT_SIZE: 0
@ -6726,7 +6700,6 @@ cmdstream[0]: 1023 dwords
- shaderdb: 0 last-baryf, 0 half, 19 full, 29 constlen
- shaderdb: 1120 cat0, 48 cat1, 551 cat2, 512 cat3, 183 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 1326 sstall, 140 (ss), 0 (sy)
+ 00000000 SP_FS_OBJ_START_HI: 0
!+ 00000100 SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 }
+ fcfcfc00 SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }
!+ 00000001 SP_FS_OUTPUT_CNTL1: { MRT = 1 }
@ -6744,7 +6717,6 @@ cmdstream[0]: 1023 dwords
+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 00000058 SP_FS_INSTRLEN: 88
!+ 011160a0 SP_IBO: 0x11160a0 base=1116000, offset=160, size=388
+ 00000000 SP_IBO_HI: 0
+ 00000000 SP_IBO_COUNT: 0
+ 00000100 HLSQ_VS_CNTL: { CONSTLEN = 0 | ENABLED }
+ 00000000 HLSQ_HS_CNTL: { CONSTLEN = 0 }
@ -6823,7 +6795,6 @@ cmdstream[0]: 1023 dwords
write RB_BLIT_DST_INFO (88d7)
RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WXYZ | COLOR_FORMAT = FMT6_8_8_8_X8_UNORM }
RB_BLIT_DST: 0x1125000
RB_BLIT_DST_HI: 0
RB_BLIT_DST_PITCH: 8704
RB_BLIT_DST_ARRAY_PITCH: 12533760
0000000001116144: 0000: 4888d785 000018a0 01125000 00000000 00000088 0002fd00
@ -6851,7 +6822,6 @@ cmdstream[0]: 1023 dwords
+ 00000000 RB_BLIT_BASE_GMEM: 0
!+ 000018a0 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WXYZ | COLOR_FORMAT = FMT6_8_8_8_X8_UNORM }
!+ 01125000 RB_BLIT_DST: 0x1125000
+ 00000000 RB_BLIT_DST_HI: 0
!+ 00000088 RB_BLIT_DST_PITCH: 8704
!+ 0002fd00 RB_BLIT_DST_ARRAY_PITCH: 12533760
!+ 00000000 RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }

182
src/freedreno/decode/cffdec.c
View file

@ -815,14 +815,60 @@ endswith(uint32_t regbase, const char *suffix)
return (s - strlen(name) + strlen(suffix)) == name;
}
void
dump_register_val(uint32_t regbase, uint32_t dword, int level)
struct regacc
regacc(struct rnn *r)
{
struct rnndecaddrinfo *info = rnn_reginfo(rnn, regbase);
if (!r)
r = rnn;
return (struct regacc){ .rnn = r };
}
/* returns true if the complete reg value has been accumulated: */
bool
regacc_push(struct regacc *r, uint32_t regbase, uint32_t dword)
{
if (r->has_dword_lo) {
/* Work around kernel devcore dumps which accidentially miss half of a 64b reg
* see: https://patchwork.freedesktop.org/series/112302/
*/
if (regbase != r->regbase + 1) {
printf("WARNING: 64b discontinuity (%x, expected %x)\n", regbase, r->regbase + 1);
r->has_dword_lo = false;
return true;
}
r->value |= ((uint64_t)dword) << 32;
r->has_dword_lo = false;
return true;
}
r->regbase = regbase;
r->value = dword;
struct rnndecaddrinfo *info = rnn_reginfo(r->rnn, regbase);
r->has_dword_lo = (info->width == 64);
/* Workaround for kernel devcore dump bugs: */
if ((info->width == 64) && endswith(regbase, "_HI")) {
printf("WARNING: 64b discontinuity (no _LO dword for %x)\n", regbase);
r->has_dword_lo = false;
}
rnn_reginfo_free(info);
return !r->has_dword_lo;
}
void
dump_register_val(struct regacc *r, int level)
{
struct rnndecaddrinfo *info = rnn_reginfo(rnn, r->regbase);
if (info && info->typeinfo) {
uint64_t gpuaddr = 0;
char *decoded = rnndec_decodeval(rnn->vc, info->typeinfo, dword);
char *decoded = rnndec_decodeval(rnn->vc, info->typeinfo, r->value);
printf("%s%s: %s", levels[level], info->name, decoded);
/* Try and figure out if we are looking at a gpuaddr.. this
@ -834,13 +880,18 @@ dump_register_val(uint32_t regbase, uint32_t dword, int level)
if (options->gpu_id >= 600) {
if (!strcmp(info->typeinfo->name, "address") ||
!strcmp(info->typeinfo->name, "waddress")) {
gpuaddr = (((uint64_t)reg_val(regbase + 1)) << 32) | dword;
gpuaddr = r->value;
}
} else if (options->gpu_id >= 500) {
if (endswith(regbase, "_HI") && endswith(regbase - 1, "_LO")) {
gpuaddr = (((uint64_t)dword) << 32) | reg_val(regbase - 1);
} else if (endswith(regbase, "_LO") && endswith(regbase + 1, "_HI")) {
gpuaddr = (((uint64_t)reg_val(regbase + 1)) << 32) | dword;
/* TODO we shouldn't rely on reg_val() since reg_set() might
* not have been called yet for the other half of the 64b reg.
* We can remove this hack once a5xx.xml is converted to reg64
* and address/waddess.
*/
if (endswith(r->regbase, "_HI") && endswith(r->regbase - 1, "_LO")) {
gpuaddr = (r->value << 32) | reg_val(r->regbase - 1);
} else if (endswith(r->regbase, "_LO") && endswith(r->regbase + 1, "_HI")) {
gpuaddr = (((uint64_t)reg_val(r->regbase + 1)) << 32) | r->value;
}
}
@ -854,28 +905,27 @@ dump_register_val(uint32_t regbase, uint32_t dword, int level)
free(decoded);
} else if (info) {
printf("%s%s: %08x\n", levels[level], info->name, dword);
printf("%s%s: %08"PRIx64"\n", levels[level], info->name, r->value);
} else {
printf("%s<%04x>: %08x\n", levels[level], regbase, dword);
printf("%s<%04x>: %08"PRIx64"\n", levels[level], r->regbase, r->value);
}
rnn_reginfo_free(info);
}
static void
dump_register(uint32_t regbase, uint32_t dword, int level)
dump_register(struct regacc *r, int level)
{
if (!quiet(3)) {
dump_register_val(regbase, dword, level);
dump_register_val(r, level);
}
for (unsigned idx = 0; type0_reg[idx].regname; idx++) {
if (type0_reg[idx].regbase == regbase) {
if (type0_reg[idx].regbase == r->regbase) {
if (type0_reg[idx].is_reg64) {
uint64_t qword = (((uint64_t)reg_val(regbase + 1)) << 32) | dword;
type0_reg[idx].fxn64(type0_reg[idx].regname, qword, level);
type0_reg[idx].fxn64(type0_reg[idx].regname, r->value, level);
} else {
type0_reg[idx].fxn(type0_reg[idx].regname, dword, level);
type0_reg[idx].fxn(type0_reg[idx].regname, (uint32_t)r->value, level);
}
break;
}
@ -892,6 +942,8 @@ static void
dump_registers(uint32_t regbase, uint32_t *dwords, uint32_t sizedwords,
int level)
{
struct regacc r = regacc(NULL);
while (sizedwords--) {
int last_summary = summary;
@ -902,7 +954,8 @@ dump_registers(uint32_t regbase, uint32_t *dwords, uint32_t sizedwords,
printl(2, "NEEDS WFI: %s (%x)\n", regname(regbase, 1), regbase);
reg_set(regbase, *dwords);
dump_register(regbase, *dwords, level);
if (regacc_push(&r, regbase, *dwords))
dump_register(&r, level);
regbase++;
dwords++;
summary = last_summary;
@ -1030,26 +1083,33 @@ __do_query(const char *primtype, uint32_t num_indices)
for (int i = 0; i < options->nquery; i++) {
uint32_t regbase = queryvals[i];
if (reg_written(regbase)) {
uint32_t lastval = reg_val(regbase);
printf("%4d: %s(%u,%u-%u,%u):%u:", draw_count, primtype, bin_x1,
bin_y1, bin_x2, bin_y2, num_indices);
if (options->gpu_id >= 500)
printf("%s:", render_mode);
printf("\t%08x", lastval);
if (lastval != lastvals[regbase]) {
printf("!");
} else {
printf(" ");
}
if (reg_rewritten(regbase)) {
printf("+");
} else {
printf(" ");
}
dump_register_val(regbase, lastval, 0);
n++;
if (!reg_written(regbase))
continue;
struct regacc r = regacc(NULL);
/* 64b regs require two successive 32b dwords: */
for (int d = 0; d < 2; d++)
if (regacc_push(&r, regbase + d, reg_val(regbase + d)))
break;
printf("%4d: %s(%u,%u-%u,%u):%u:", draw_count, primtype, bin_x1,
bin_y1, bin_x2, bin_y2, num_indices);
if (options->gpu_id >= 500)
printf("%s:", render_mode);
printf("\t%08"PRIx64, r.value);
if (r.value != lastvals[regbase]) {
printf("!");
} else {
printf(" ");
}
if (reg_rewritten(regbase)) {
printf("+");
} else {
printf(" ");
}
dump_register_val(&r, 0);
n++;
}
if (n > 1)
@ -1157,9 +1217,10 @@ static void
cp_wide_reg_write(uint32_t *dwords, uint32_t sizedwords, int level)
{
uint32_t reg = dwords[0] & 0xffff;
int i;
for (i = 1; i < sizedwords; i++) {
dump_register(reg, dwords[i], level + 1);
struct regacc r = regacc(NULL);
for (int i = 1; i < sizedwords; i++) {
if (regacc_push(&r, reg, dwords[i]))
dump_register(&r, level + 1);
reg_set(reg, dwords[i]);
reg++;
}
@ -1831,8 +1892,14 @@ dump_register_summary(int level)
in_summary = true;
struct regacc r = regacc(NULL);
/* dump current state of registers: */
printl(2, "%sdraw[%i] register values\n", levels[level], draw_count);
bool changed = false;
bool written = false;
for (i = 0; i < regcnt(); i++) {
uint32_t regbase = i;
uint32_t lastval = reg_val(regbase);
@ -1842,19 +1909,29 @@ dump_register_summary(int level)
if (!reg_written(regbase))
continue;
if (lastval != lastvals[regbase]) {
printl(2, "!");
changed |= true;
lastvals[regbase] = lastval;
} else {
printl(2, " ");
}
if (reg_rewritten(regbase)) {
printl(2, "+");
} else {
printl(2, " ");
written |= true;
}
printl(2, "\t%08x", lastval);
if (!quiet(2)) {
dump_register(regbase, lastval, level);
if (regacc_push(&r, regbase, lastval)) {
if (changed) {
printl(2, "!");
} else {
printl(2, " ");
}
if (written) {
printl(2, "+");
} else {
printl(2, " ");
}
printl(2, "\t%08"PRIx64, r.value);
dump_register(&r, level);
changed = written = false;
}
}
}
@ -2616,8 +2693,11 @@ cp_context_reg_bunch(uint32_t *dwords, uint32_t sizedwords, int level)
bool saved_summary = summary;
summary = false;
struct regacc r = regacc(NULL);
for (i = 0; i < sizedwords; i += 2) {
dump_register(dwords[i + 0], dwords[i + 1], level + 1);
if (regacc_push(&r, dwords[i + 0], dwords[i + 1]))
dump_register(&r, level + 1);
reg_set(dwords[i + 0], dwords[i + 1]);
}
@ -2629,7 +2709,9 @@ cp_reg_write(uint32_t *dwords, uint32_t sizedwords, int level)
{
uint32_t reg = dwords[1] & 0xffff;
dump_register(reg, dwords[2], level + 1);
struct regacc r = regacc(NULL);
if (regacc_push(&r, reg, dwords[2]))
dump_register(&r, level + 1);
reg_set(reg, dwords[2]);
}

29
src/freedreno/decode/cffdec.h
View file

@ -81,6 +81,33 @@ struct cffdec_options {
} ibs[4];
};
/**
* A helper to deal with 64b registers by accumulating the lo/hi 32b
* dwords. Example usage:
*
* struct regacc r = regacc(rnn);
*
* for (dword in dwords) {
* if (regacc_push(&r, regbase, dword)) {
* printf("\t%08x"PRIx64", r.value);
* dump_register_val(r.regbase, r.value, 0);
* }
* regbase++;
* }
*
* It is expected that 64b regs will come in pairs of <lo, hi>.
*/
struct regacc {
uint32_t regbase;
uint64_t value;
/* private: */
struct rnn *rnn;
bool has_dword_lo;
};
struct regacc regacc(struct rnn *rnn);
bool regacc_push(struct regacc *regacc, uint32_t regbase, uint32_t dword);
void printl(int lvl, const char *fmt, ...);
const char *pktname(unsigned opc);
uint32_t regbase(const char *name);
@ -91,7 +118,7 @@ uint32_t reg_val(uint32_t regbase);
void reg_set(uint32_t regbase, uint32_t val);
void reset_regs(void);
void cffdec_init(const struct cffdec_options *options);
void dump_register_val(uint32_t regbase, uint32_t dword, int level);
void dump_register_val(struct regacc *r, int level);
void dump_commands(uint32_t *dwords, uint32_t sizedwords, int level);
/*

10
src/freedreno/decode/crashdec-mempool.c
View file

@ -29,6 +29,12 @@ static void
dump_mem_pool_reg_write(unsigned reg, uint32_t data, unsigned context,
bool pipe)
{
/* TODO deal better somehow w/ 64b regs: */
struct regacc r = {
.rnn = pipe ? rnn_pipe : NULL,
.regbase = reg,
.value = data,
};
if (pipe) {
struct rnndecaddrinfo *info = rnn_reginfo(rnn_pipe, reg);
printf("\t\twrite %s (%02x) pipe\n", info->name, reg);
@ -37,12 +43,12 @@ dump_mem_pool_reg_write(unsigned reg, uint32_t data, unsigned context,
/* registers that ignore their payload */
} else {
printf("\t\t\t");
dump_register(rnn_pipe, reg, data);
dump_register(&r);
}
rnn_reginfo_free(info);
} else {
printf("\t\twrite %s (%05x) context %d\n", regname(reg, 1), reg, context);
dump_register_val(reg, data, 2);
dump_register_val(&r, 2);
}
}

42
src/freedreno/decode/crashdec.c
View file

@ -458,16 +458,16 @@ decode_bos(void)
*/
void
dump_register(struct rnn *rnn, uint32_t offset, uint32_t value)
dump_register(struct regacc *r)
{
struct rnndecaddrinfo *info = rnn_reginfo(rnn, offset);
struct rnndecaddrinfo *info = rnn_reginfo(r->rnn, r->regbase);
if (info && info->typeinfo) {
char *decoded = rnndec_decodeval(rnn->vc, info->typeinfo, value);
char *decoded = rnndec_decodeval(r->rnn->vc, info->typeinfo, r->value);
printf("%s: %s\n", info->name, decoded);
} else if (info) {
printf("%s: %08x\n", info->name, value);
printf("%s: %08"PRIx64"\n", info->name, r->value);
} else {
printf("<%04x>: %08x\n", offset, value);
printf("<%04x>: %08"PRIx64"\n", r->regbase, r->value);
}
rnn_reginfo_free(info);
}
@ -475,25 +475,33 @@ dump_register(struct rnn *rnn, uint32_t offset, uint32_t value)
static void
decode_gmu_registers(void)
{
struct regacc r = regacc(rnn_gmu);
foreach_line_in_section (line) {
uint32_t offset, value;
parseline(line, " - { offset: %x, value: %x }", &offset, &value);
printf("\t%08x\t", value);
dump_register(rnn_gmu, offset / 4, value);
if (regacc_push(&r, offset / 4, value)) {
printf("\t%08"PRIx64"\t", r.value);
dump_register(&r);
}
}
}
static void
decode_registers(void)
{
struct regacc r = regacc(NULL);
foreach_line_in_section (line) {
uint32_t offset, value;
parseline(line, " - { offset: %x, value: %x }", &offset, &value);
reg_set(offset / 4, value);
printf("\t%08x", value);
dump_register_val(offset / 4, value, 0);
if (regacc_push(&r, offset / 4, value)) {
printf("\t%08"PRIx64, r.value);
dump_register_val(&r, 0);
}
}
}
@ -501,6 +509,8 @@ decode_registers(void)
static void
decode_clusters(void)
{
struct regacc r = regacc(NULL);
foreach_line_in_section (line) {
if (startswith(line, " - cluster-name:") ||
startswith(line, " - context:")) {
@ -511,8 +521,10 @@ decode_clusters(void)
uint32_t offset, value;
parseline(line, " - { offset: %x, value: %x }", &offset, &value);
printf("\t%08x", value);
dump_register_val(offset / 4, value, 0);
if (regacc_push(&r, offset / 4, value)) {
printf("\t%08"PRIx64, r.value);
dump_register_val(&r, 0);
}
}
}
@ -550,14 +562,18 @@ dump_control_regs(uint32_t *regs)
if (!rnn_control)
return;
struct regacc r = regacc(rnn_control);
/* Control regs 0x100-0x17f are a scratch space to be used by the
* firmware however it wants, unlike lower regs which involve some
* fixed-function units. Therefore only these registers get dumped
* directly.
*/
for (uint32_t i = 0; i < 0x80; i++) {
printf("\t%08x\t", regs[i]);
dump_register(rnn_control, i + 0x100, regs[i]);
if (regacc_push(&r, i + 0x100, regs[i])) {
printf("\t%08"PRIx64"\t", r.value);
dump_register(&r);
}
}
}

2
src/freedreno/decode/crashdec.h
View file

@ -84,7 +84,7 @@ is_gmu_legacy(void)
}
}
void dump_register(struct rnn *rnn, uint32_t offset, uint32_t value);
void dump_register(struct regacc *r);
void dump_cp_mem_pool(uint32_t *mempool);
struct a6xx_hfi_state {