From ffb77c8be616556a50ba1dbb93182d96b8a5ead4 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 29 Dec 2022 11:39:05 -0800 Subject: [PATCH] freedreno/decode: Improved reg64 decoding This also (other than for an a5xx hack) gets rid of relying on type0_reg_vals which isn't updated in all paths. Signed-off-by: Rob Clark Part-of: --- src/freedreno/.gitlab-ci/reference/crash.log | 575 +++++------------- ...exed.indirect_draw_count.triangle_list.log | 38 -- .../.gitlab-ci/reference/fd-clouds.log | 30 - src/freedreno/decode/cffdec.c | 182 ++++-- src/freedreno/decode/cffdec.h | 29 +- src/freedreno/decode/crashdec-mempool.c | 10 +- src/freedreno/decode/crashdec.c | 42 +- src/freedreno/decode/crashdec.h | 2 +- 8 files changed, 337 insertions(+), 571 deletions(-) diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log index 01acc8702d5..ee6e713b89d 100644 --- a/src/freedreno/.gitlab-ci/reference/crash.log +++ b/src/freedreno/.gitlab-ci/reference/crash.log @@ -615,12 +615,10 @@ registers: 0c000020 RBBM_PRIMCTR_9_HI: 0xc000020 80820000 RBBM_PRIMCTR_10_LO: 0x80820000 40000800 RBBM_PRIMCTR_10_HI: 0x40000800 - 00001000 CP_RB_BASE: 0x1000 - 00010000 CP_RB_BASE+0x1: 0x10000 + 1000000001000 CP_RB_BASE: 0x1000000001000 0000020c CP_RB_CNTL: 0x20c 00000000 0x803: 00000000 - 00000000 CP_RB_RPTR_ADDR: 0 - 00010000 CP_RB_RPTR_ADDR+0x1: 0x10000 + 1000000000000 CP_RB_RPTR_ADDR: 0x1000000000000 00000038 CP_RB_RPTR: 0x38 00000038 CP_RB_WPTR: 0x38 00000001 CP_SQE_CNTL: 0x1 @@ -634,8 +632,7 @@ registers: 00000000 CP_PROTECT_STATUS: 0 00000707 0x826: 00000707 00000001 0x827: 00000001 - 00009000 CP_SQE_INSTR_BASE: 0x9000 - 00010000 CP_SQE_INSTR_BASE+0x1: 0x10000 + 1000000009000 CP_SQE_INSTR_BASE: 0x1000000009000 00000000 0x832: 00000000 00000000 0x833: 00000000 00000000 CP_MISC_CNTL: 0 @@ -688,13 +685,9 @@ registers: 00000002 CP_SCRATCH[0x7].REG: 2 00000000 CP_CONTEXT_SWITCH_CNTL: 0 00000000 CP_CONTEXT_SWITCH_SMMU_INFO: 0 - 00000000 CP_CONTEXT_SWITCH_SMMU_INFO+0x1: 0 00000000 CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR: 0 - 00000000 CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR+0x1: 0 00000000 CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR: 0 - 00000000 CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR+0x1: 0 00000000 CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR: 0 - 00000000 CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR+0x1: 0 00000000 0x8a9: 00000000 00000000 0x8aa: 00000000 00000000 0x8ab: 00000000 @@ -721,8 +714,7 @@ registers: 00000000 0x8f1: 00000000 00000000 0x8f2: 00000000 00000000 0x8f3: 00000000 - 00011000 CP_CRASH_SCRIPT_BASE: 0x11000 - 00010000 CP_CRASH_SCRIPT_BASE+0x1: 0x10000 + 1000000011000 CP_CRASH_SCRIPT_BASE: 0x1000000011000 00000001 CP_CRASH_DUMP_CNTL: 0x1 00000001 CP_CRASH_DUMP_STATUS: 0x1 00000033 CP_SQE_STAT_ADDR: 0x33 @@ -735,20 +727,15 @@ registers: 00000007 CP_MEM_POOL_DBG_DATA: 0x7 00006000 CP_SQE_UCODE_DBG_ADDR: 0x6000 00000000 CP_SQE_UCODE_DBG_DATA: 0 - 00000000 CP_IB1_BASE: 0 - 00000001 CP_IB1_BASE+0x1: 0x1 + 100000000 CP_IB1_BASE: 0x100000000 00000000 CP_IB1_REM_SIZE: 0 00000000 CP_IB2_BASE: 0 - 00000000 CP_IB2_BASE+0x1: 0 00000000 CP_IB2_REM_SIZE: 0 00000000 CP_SDS_BASE: 0 - 00000000 CP_SDS_BASE+0x1: 0 00000000 CP_SDS_REM_SIZE: 0 - 0000c600 CP_MRB_BASE: 0xc600 - 00010000 CP_MRB_BASE+0x1: 0x10000 + 100000000c600 CP_MRB_BASE: 0x100000000c600 00000000 CP_MRB_REM_SIZE: 0 00000000 CP_VSD_BASE: 0 - 00000000 CP_VSD_BASE+0x1: 0 00000000 0x936: 00000000 00800000 0x937: 00800000 00000000 0x938: 00000000 @@ -771,7 +758,6 @@ registers: 00000000 CP_MRQ_MRB_STAT: { REM = 0 } 00000000 0x94d: 00000000 00305efe CP_ALWAYS_ON_COUNTER: 0x305efe - 00000000 CP_ALWAYS_ON_COUNTER+0x1: 0 00225162 0x982: 00225162 00000000 0x983: 00000000 00000000 0x984: 00000000 @@ -823,7 +809,6 @@ registers: 00000001 VSC_ADDR_MODE_CNTL: ADDR_64B 00000101 VSC_BIN_SIZE: { WIDTH = 32 | HEIGHT = 16 } 00000000 VSC_DRAW_STRM_SIZE_ADDRESS: 0 - 00000000 VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0 00000000 VSC_BIN_COUNT: { NX = 0 | NY = 0 } 00000000 VSC_PIPE_CONFIG[0].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } 00000000 VSC_PIPE_CONFIG[0x1].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } @@ -858,11 +843,9 @@ registers: 00000000 VSC_PIPE_CONFIG[0x1e].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } 00000000 VSC_PIPE_CONFIG[0x1f].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } 00000000 VSC_PRIM_STRM_ADDRESS: 0 - 00000000 VSC_PRIM_STRM_ADDRESS_HI: 0 00000000 VSC_PRIM_STRM_PITCH: 0 00000000 VSC_PRIM_STRM_LIMIT: 0 00000000 VSC_DRAW_STRM_ADDRESS: 0 - 00000000 VSC_DRAW_STRM_ADDRESS_HI: 0 00000000 VSC_DRAW_STRM_PITCH: 0 00000000 VSC_DRAW_STRM_LIMIT: 0 00000000 VSC_STATE[0].REG: 0 @@ -1032,16 +1015,11 @@ registers: 00000000 0xe02: 00000000 00000000 0xe03: 00000000 00000000 0xe04: 00000000 - ffffffc0 UCHE_WRITE_RANGE_MAX: 0xffffffc0 - 0001ffff UCHE_WRITE_RANGE_MAX+0x1: 0x1ffff - fffff000 UCHE_WRITE_THRU_BASE: 0xfffff000 - 0001ffff UCHE_WRITE_THRU_BASE+0x1: 0x1ffff - fffff000 UCHE_TRAP_BASE: 0xfffff000 - 0001ffff UCHE_TRAP_BASE+0x1: 0x1ffff + 1ffffffffffc0 UCHE_WRITE_RANGE_MAX: 0x1ffffffffffc0 + 1fffffffff000 UCHE_WRITE_THRU_BASE: 0x1fffffffff000 + 1fffffffff000 UCHE_TRAP_BASE: 0x1fffffffff000 00100000 UCHE_GMEM_RANGE_MIN: 0x100000 - 00000000 UCHE_GMEM_RANGE_MIN+0x1: 0 001ff000 UCHE_GMEM_RANGE_MAX: 0x1ff000 - 00000000 UCHE_GMEM_RANGE_MAX+0x1: 0 00000000 0xe10: 00000000 00000000 0xe11: 00000000 00000000 UCHE_UNKNOWN_0E12: 0 @@ -1126,11 +1104,9 @@ registers: 00000001 PC_ADDR_MODE_CNTL: ADDR_64B 00000000 0x9e03: 00000000 00000000 PC_DRAW_INDX_BASE: 0 - 00000000 PC_DRAW_INDX_BASE+0x1: 0 00000000 PC_DRAW_FIRST_INDX: 0 00000000 PC_DRAW_MAX_INDICES: 0 00000000 PC_TESSFACTOR_ADDR: 0 - 00000000 PC_TESSFACTOR_ADDR_HI: 0 00000001 0x9e0a: 00000001 00004080 PC_DRAW_INITIATOR: { PRIM_TYPE = DI_PT_NONE | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS | 0x4000 } 00000000 PC_DRAW_NUM_INSTANCES: 0 @@ -1138,9 +1114,7 @@ registers: 00000000 0x9e0e: 00000000 00010000 PC_VSTREAM_CONTROL: { VSC_SIZE = 1 | VSC_N = 0 } 00000000 PC_BIN_PRIM_STRM: 0 - 00000000 PC_BIN_PRIM_STRM_HI: 0 00000000 PC_BIN_DRAW_STRM: 0 - 00000000 PC_BIN_DRAW_STRM_HI: 0 00000000 0x9e16: 00000000 00000000 0x9e19: 00000000 00000000 PC_VISIBILITY_OVERRIDE: { 0 } @@ -2969,15 +2943,10 @@ indexed-registers: 23332200 0x10e: 23332200 30664402 0x10f: 30664402 00000000 SAVE_REGISTER_SMMU_INFO: 0 - 00000000 SAVE_REGISTER_SMMU_INFO+0x1: 0 00000000 SAVE_REGISTER_PRIV_NON_SECURE: 0 - 00000000 SAVE_REGISTER_PRIV_NON_SECURE+0x1: 0 00000000 SAVE_REGISTER_PRIV_SECURE: 0 - 00000000 SAVE_REGISTER_PRIV_SECURE+0x1: 0 00000000 SAVE_REGISTER_NON_PRIV: 0 - 00000000 SAVE_REGISTER_NON_PRIV+0x1: 0 00000000 SAVE_REGISTER_COUNTER: 0 - 00000000 SAVE_REGISTER_COUNTER+0x1: 0 00000000 0x11a: 00000000 00000000 0x11b: 00000000 00000000 0x11c: 00000000 @@ -5473,10 +5442,8 @@ clusters: 00000000 GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER } 00000000 GRAS_LRZ_MRT_BUF_INFO_0: { COLOR_FORMAT = 0 } 00000000 GRAS_LRZ_BUFFER_BASE: 0 - 00000000 GRAS_LRZ_BUFFER_BASE_HI: 0 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0 - 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0 00000000 GRAS_SAMPLE_CNTL: { 0 } 00000000 GRAS_UNKNOWN_8110: 0 00000000 GRAS_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_RAW | RASTER_MODE = TYPE_TILED } @@ -5718,10 +5685,8 @@ clusters: 00000000 GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER } 00000000 GRAS_LRZ_MRT_BUF_INFO_0: { COLOR_FORMAT = 0 } 00000000 GRAS_LRZ_BUFFER_BASE: 0 - 00000000 GRAS_LRZ_BUFFER_BASE_HI: 0 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0 - 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0 00000000 GRAS_SAMPLE_CNTL: { 0 } 00000000 GRAS_UNKNOWN_8110: 0 00000000 GRAS_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_RAW | RASTER_MODE = TYPE_TILED } @@ -5767,7 +5732,6 @@ clusters: 00000000 RB_MRT[0].PITCH: 0 00000000 RB_MRT[0].ARRAY_PITCH: 0 00000000 RB_MRT[0].BASE: 0 - 00000000 RB_MRT[0].BASE_HI: 0 00000000 RB_MRT[0].BASE_GMEM: 0 00000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } 00000000 RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } @@ -5775,7 +5739,6 @@ clusters: 00000000 RB_MRT[0x1].PITCH: 0 00000000 RB_MRT[0x1].ARRAY_PITCH: 0 00000000 RB_MRT[0x1].BASE: 0 - 00000000 RB_MRT[0x1].BASE_HI: 0 00000000 RB_MRT[0x1].BASE_GMEM: 0 00000000 RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } 00000000 RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } @@ -5783,7 +5746,6 @@ clusters: 00000000 RB_MRT[0x2].PITCH: 0 00000000 RB_MRT[0x2].ARRAY_PITCH: 0 00000000 RB_MRT[0x2].BASE: 0 - 00000000 RB_MRT[0x2].BASE_HI: 0 00000000 RB_MRT[0x2].BASE_GMEM: 0 00000000 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } 00000000 RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } @@ -5791,7 +5753,6 @@ clusters: 00000000 RB_MRT[0x3].PITCH: 0 00000000 RB_MRT[0x3].ARRAY_PITCH: 0 00000000 RB_MRT[0x3].BASE: 0 - 00000000 RB_MRT[0x3].BASE_HI: 0 00000000 RB_MRT[0x3].BASE_GMEM: 0 00000000 RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } 00000000 RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } @@ -5799,7 +5760,6 @@ clusters: 00000000 RB_MRT[0x4].PITCH: 0 00000000 RB_MRT[0x4].ARRAY_PITCH: 0 00000000 RB_MRT[0x4].BASE: 0 - 00000000 RB_MRT[0x4].BASE_HI: 0 00000000 RB_MRT[0x4].BASE_GMEM: 0 00000000 RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } 00000000 RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } @@ -5807,7 +5767,6 @@ clusters: 00000000 RB_MRT[0x5].PITCH: 0 00000000 RB_MRT[0x5].ARRAY_PITCH: 0 00000000 RB_MRT[0x5].BASE: 0 - 00000000 RB_MRT[0x5].BASE_HI: 0 00000000 RB_MRT[0x5].BASE_GMEM: 0 00000000 RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } 00000000 RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } @@ -5815,7 +5774,6 @@ clusters: 00000000 RB_MRT[0x6].PITCH: 0 00000000 RB_MRT[0x6].ARRAY_PITCH: 0 00000000 RB_MRT[0x6].BASE: 0 - 00000000 RB_MRT[0x6].BASE_HI: 0 00000000 RB_MRT[0x6].BASE_GMEM: 0 00000000 RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } 00000000 RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } @@ -5823,7 +5781,6 @@ clusters: 00000000 RB_MRT[0x7].PITCH: 0 00000000 RB_MRT[0x7].ARRAY_PITCH: 0 00000000 RB_MRT[0x7].BASE: 0 - 00000000 RB_MRT[0x7].BASE_HI: 0 00000000 RB_MRT[0x7].BASE_GMEM: 0 00000000 RB_BLEND_RED_F32: 0.000000 00000000 RB_BLEND_GREEN_F32: 0.000000 @@ -5837,7 +5794,6 @@ clusters: 00000000 RB_DEPTH_BUFFER_PITCH: 0 00000000 RB_DEPTH_BUFFER_ARRAY_PITCH: 0 00000000 RB_DEPTH_BUFFER_BASE: 0 - 00000000 RB_DEPTH_BUFFER_BASE_HI: 0 00000000 RB_DEPTH_BUFFER_BASE_GMEM: 0 00000000 RB_Z_BOUNDS_MIN: 0.000000 00000000 RB_Z_BOUNDS_MAX: 0.000000 @@ -5846,7 +5802,6 @@ clusters: 00000000 RB_STENCIL_BUFFER_PITCH: 0 00000000 RB_STENCIL_BUFFER_ARRAY_PITCH: 0 00000000 RB_STENCIL_BUFFER_BASE: 0 - 00000000 RB_STENCIL_BUFFER_BASE_HI: 0 00000000 RB_STENCIL_BUFFER_BASE_GMEM: 0 00000000 RB_STENCILREF: { REF = 0 | BFREF = 0 } 00000000 RB_STENCILMASK: { MASK = 0 | BFMASK = 0 } @@ -5865,11 +5820,9 @@ clusters: 00000000 RB_BLIT_BASE_GMEM: 0 00004100 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_32_32_32_32_FLOAT } 00000000 RB_BLIT_DST: 0 - 00000000 RB_BLIT_DST_HI: 0 00000000 RB_BLIT_DST_PITCH: 0 00000000 RB_BLIT_DST_ARRAY_PITCH: 0 00000000 RB_BLIT_FLAG_DST: 0 - 00000000 RB_BLIT_FLAG_DST_HI: 0 00000000 RB_BLIT_FLAG_DST_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 RB_BLIT_CLEAR_COLOR_DW0: 0 00000000 RB_BLIT_CLEAR_COLOR_DW1: 0 @@ -5877,29 +5830,23 @@ clusters: 00000000 RB_BLIT_CLEAR_COLOR_DW3: 0 000000f2 RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf | LAST = 0 | BUFFER_ID = 0 } 00000000 RB_DEPTH_FLAG_BUFFER_BASE: 0 - 00000000 RB_DEPTH_FLAG_BUFFER_BASE_HI: 0 00000000 RB_DEPTH_FLAG_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 RB_MRT_FLAG_BUFFER[0].ADDR: 0 - 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0 00000000 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 RB_MRT_FLAG_BUFFER[0x1].ADDR: 0 - 00000000 RB_MRT_FLAG_BUFFER[0x1].ADDR_HI: 0 00000000 RB_MRT_FLAG_BUFFER[0x1].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 RB_MRT_FLAG_BUFFER[0x2].ADDR: 0 - 00000000 RB_MRT_FLAG_BUFFER[0x2].ADDR_HI: 0 00000000 RB_MRT_FLAG_BUFFER[0x2].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } +WARNING: 64b discontinuity (890f, expected 890d) 00000000 RB_MRT_FLAG_BUFFER[0x3].ADDR: 0 - 00000000 RB_MRT_FLAG_BUFFER[0x4].ADDR: 0 +WARNING: 64b discontinuity (no _LO dword for 8910) 00000000 RB_MRT_FLAG_BUFFER[0x4].ADDR_HI: 0 00000000 RB_MRT_FLAG_BUFFER[0x4].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 RB_MRT_FLAG_BUFFER[0x5].ADDR: 0 - 00000000 RB_MRT_FLAG_BUFFER[0x5].ADDR_HI: 0 00000000 RB_MRT_FLAG_BUFFER[0x5].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 RB_MRT_FLAG_BUFFER[0x6].ADDR: 0 - 00000000 RB_MRT_FLAG_BUFFER[0x6].ADDR_HI: 0 00000000 RB_MRT_FLAG_BUFFER[0x6].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 RB_MRT_FLAG_BUFFER[0x7].ADDR: 0 - 00000000 RB_MRT_FLAG_BUFFER[0x7].ADDR_HI: 0 00000000 RB_MRT_FLAG_BUFFER[0x7].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_RAW | RASTER_MODE = TYPE_TILED } 00000000 RB_2D_UNKNOWN_8C01: 0 @@ -5914,13 +5861,10 @@ clusters: 00000000 0x8c10: 00000000 00000000 RB_2D_DST_INFO: { COLOR_FORMAT = 0 | TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX | SAMPLES = MSAA_ONE } 00000000 RB_2D_DST: 0 - 00000000 RB_2D_DST_HI: 0 00000000 RB_2D_DST_PITCH: 0 00000000 RB_2D_DST_PLANE1: 0 - 00000000 RB_2D_DST_PLANE1_HI: 0 00000000 RB_2D_DST_PLANE_PITCH: 0 00000000 RB_2D_DST_PLANE2: 0 - 00000000 RB_2D_DST_PLANE2_HI: 0 00000000 0x8c26: 00000000 00000000 0x8c27: 00000000 00000000 0x8c28: 00000000 @@ -5965,7 +5909,6 @@ clusters: 00000000 RB_MRT[0].PITCH: 0 00000000 RB_MRT[0].ARRAY_PITCH: 0 00000000 RB_MRT[0].BASE: 0 - 00000000 RB_MRT[0].BASE_HI: 0 00000000 RB_MRT[0].BASE_GMEM: 0 00000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } 00000000 RB_MRT[0x1].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } @@ -5973,7 +5916,6 @@ clusters: 00000000 RB_MRT[0x1].PITCH: 0 00000000 RB_MRT[0x1].ARRAY_PITCH: 0 00000000 RB_MRT[0x1].BASE: 0 - 00000000 RB_MRT[0x1].BASE_HI: 0 00000000 RB_MRT[0x1].BASE_GMEM: 0 00000000 RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } 00000000 RB_MRT[0x2].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } @@ -5981,7 +5923,6 @@ clusters: 00000000 RB_MRT[0x2].PITCH: 0 00000000 RB_MRT[0x2].ARRAY_PITCH: 0 00000000 RB_MRT[0x2].BASE: 0 - 00000000 RB_MRT[0x2].BASE_HI: 0 00000000 RB_MRT[0x2].BASE_GMEM: 0 00000000 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } 00000000 RB_MRT[0x3].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } @@ -5989,7 +5930,6 @@ clusters: 00000000 RB_MRT[0x3].PITCH: 0 00000000 RB_MRT[0x3].ARRAY_PITCH: 0 00000000 RB_MRT[0x3].BASE: 0 - 00000000 RB_MRT[0x3].BASE_HI: 0 00000000 RB_MRT[0x3].BASE_GMEM: 0 00000000 RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } 00000000 RB_MRT[0x4].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } @@ -5997,7 +5937,6 @@ clusters: 00000000 RB_MRT[0x4].PITCH: 0 00000000 RB_MRT[0x4].ARRAY_PITCH: 0 00000000 RB_MRT[0x4].BASE: 0 - 00000000 RB_MRT[0x4].BASE_HI: 0 00000000 RB_MRT[0x4].BASE_GMEM: 0 00000000 RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } 00000000 RB_MRT[0x5].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } @@ -6005,7 +5944,6 @@ clusters: 00000000 RB_MRT[0x5].PITCH: 0 00000000 RB_MRT[0x5].ARRAY_PITCH: 0 00000000 RB_MRT[0x5].BASE: 0 - 00000000 RB_MRT[0x5].BASE_HI: 0 00000000 RB_MRT[0x5].BASE_GMEM: 0 00000000 RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } 00000000 RB_MRT[0x6].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } @@ -6013,7 +5951,6 @@ clusters: 00000000 RB_MRT[0x6].PITCH: 0 00000000 RB_MRT[0x6].ARRAY_PITCH: 0 00000000 RB_MRT[0x6].BASE: 0 - 00000000 RB_MRT[0x6].BASE_HI: 0 00000000 RB_MRT[0x6].BASE_GMEM: 0 00000000 RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 } 00000000 RB_MRT[0x7].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_ZERO | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_ZERO } @@ -6021,7 +5958,6 @@ clusters: 00000000 RB_MRT[0x7].PITCH: 0 00000000 RB_MRT[0x7].ARRAY_PITCH: 0 00000000 RB_MRT[0x7].BASE: 0 - 00000000 RB_MRT[0x7].BASE_HI: 0 00000000 RB_MRT[0x7].BASE_GMEM: 0 00000000 RB_BLEND_RED_F32: 0.000000 00000000 RB_BLEND_GREEN_F32: 0.000000 @@ -6035,7 +5971,6 @@ clusters: 00000000 RB_DEPTH_BUFFER_PITCH: 0 00000000 RB_DEPTH_BUFFER_ARRAY_PITCH: 0 00000000 RB_DEPTH_BUFFER_BASE: 0 - 00000000 RB_DEPTH_BUFFER_BASE_HI: 0 00000000 RB_DEPTH_BUFFER_BASE_GMEM: 0 00000000 RB_Z_BOUNDS_MIN: 0.000000 00000000 RB_Z_BOUNDS_MAX: 0.000000 @@ -6044,7 +5979,6 @@ clusters: 00000000 RB_STENCIL_BUFFER_PITCH: 0 00000000 RB_STENCIL_BUFFER_ARRAY_PITCH: 0 00000000 RB_STENCIL_BUFFER_BASE: 0 - 00000000 RB_STENCIL_BUFFER_BASE_HI: 0 00000000 RB_STENCIL_BUFFER_BASE_GMEM: 0 00000000 RB_STENCILREF: { REF = 0 | BFREF = 0 } 00000000 RB_STENCILMASK: { MASK = 0 | BFMASK = 0 } @@ -6063,11 +5997,9 @@ clusters: 00000000 RB_BLIT_BASE_GMEM: 0 00004100 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_32_32_32_32_FLOAT } 00000000 RB_BLIT_DST: 0 - 00000000 RB_BLIT_DST_HI: 0 00000000 RB_BLIT_DST_PITCH: 0 00000000 RB_BLIT_DST_ARRAY_PITCH: 0 00000000 RB_BLIT_FLAG_DST: 0 - 00000000 RB_BLIT_FLAG_DST_HI: 0 00000000 RB_BLIT_FLAG_DST_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 RB_BLIT_CLEAR_COLOR_DW0: 0 00000000 RB_BLIT_CLEAR_COLOR_DW1: 0 @@ -6075,29 +6007,23 @@ clusters: 00000000 RB_BLIT_CLEAR_COLOR_DW3: 0 000000f2 RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf | LAST = 0 | BUFFER_ID = 0 } 00000000 RB_DEPTH_FLAG_BUFFER_BASE: 0 - 00000000 RB_DEPTH_FLAG_BUFFER_BASE_HI: 0 00000000 RB_DEPTH_FLAG_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 RB_MRT_FLAG_BUFFER[0].ADDR: 0 - 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0 00000000 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 RB_MRT_FLAG_BUFFER[0x1].ADDR: 0 - 00000000 RB_MRT_FLAG_BUFFER[0x1].ADDR_HI: 0 00000000 RB_MRT_FLAG_BUFFER[0x1].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 RB_MRT_FLAG_BUFFER[0x2].ADDR: 0 - 00000000 RB_MRT_FLAG_BUFFER[0x2].ADDR_HI: 0 00000000 RB_MRT_FLAG_BUFFER[0x2].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } +WARNING: 64b discontinuity (890f, expected 890d) 00000000 RB_MRT_FLAG_BUFFER[0x3].ADDR: 0 - 00000000 RB_MRT_FLAG_BUFFER[0x4].ADDR: 0 +WARNING: 64b discontinuity (no _LO dword for 8910) 00000000 RB_MRT_FLAG_BUFFER[0x4].ADDR_HI: 0 00000000 RB_MRT_FLAG_BUFFER[0x4].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 RB_MRT_FLAG_BUFFER[0x5].ADDR: 0 - 00000000 RB_MRT_FLAG_BUFFER[0x5].ADDR_HI: 0 00000000 RB_MRT_FLAG_BUFFER[0x5].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 RB_MRT_FLAG_BUFFER[0x6].ADDR: 0 - 00000000 RB_MRT_FLAG_BUFFER[0x6].ADDR_HI: 0 00000000 RB_MRT_FLAG_BUFFER[0x6].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 RB_MRT_FLAG_BUFFER[0x7].ADDR: 0 - 00000000 RB_MRT_FLAG_BUFFER[0x7].ADDR_HI: 0 00000000 RB_MRT_FLAG_BUFFER[0x7].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_RAW | RASTER_MODE = TYPE_TILED } 00000000 RB_2D_UNKNOWN_8C01: 0 @@ -6112,13 +6038,10 @@ clusters: 00000000 0x8c10: 00000000 00000000 RB_2D_DST_INFO: { COLOR_FORMAT = 0 | TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX | SAMPLES = MSAA_ONE } 00000000 RB_2D_DST: 0 - 00000000 RB_2D_DST_HI: 0 00000000 RB_2D_DST_PITCH: 0 00000000 RB_2D_DST_PLANE1: 0 - 00000000 RB_2D_DST_PLANE1_HI: 0 00000000 RB_2D_DST_PLANE_PITCH: 0 00000000 RB_2D_DST_PLANE2: 0 - 00000000 RB_2D_DST_PLANE2_HI: 0 00000000 0x8c26: 00000000 00000000 0x8c27: 00000000 00000000 0x8c28: 00000000 @@ -6137,12 +6060,11 @@ clusters: - context: 0 00000000 RB_UNKNOWN_88F0: 0 00000000 RB_UNK_FLAG_BUFFER_BASE: 0 - 00000000 RB_UNK_FLAG_BUFFER_BASE_HI: 0 00000000 RB_UNK_FLAG_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } +WARNING: 64b discontinuity (no _LO dword for 890d) 00000000 RB_MRT_FLAG_BUFFER[0x3].ADDR_HI: 0 00000000 RB_MRT_FLAG_BUFFER[0x3].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 RB_SAMPLE_COUNT_ADDR: 0 - 00000000 RB_SAMPLE_COUNT_ADDR_HI: 0 00000000 0x8bf0: 00000000 00000000 0x8bf1: 00000000 00000000 0x8c02: 00000000 @@ -6158,20 +6080,17 @@ clusters: 00000000 0x8c15: 00000000 00000000 0x8c16: 00000000 00000000 RB_2D_DST_FLAGS: 0 - 00000000 RB_2D_DST_FLAGS_HI: 0 00000000 RB_2D_DST_FLAGS_PITCH: 0 00000000 RB_2D_DST_FLAGS_PLANE: 0 - 00000000 RB_2D_DST_FLAGS_PLANE_HI: 0 00000000 RB_2D_DST_FLAGS_PLANE_PITCH: 0 - context: 1 00000000 RB_UNKNOWN_88F0: 0 00000000 RB_UNK_FLAG_BUFFER_BASE: 0 - 00000000 RB_UNK_FLAG_BUFFER_BASE_HI: 0 00000000 RB_UNK_FLAG_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } +WARNING: 64b discontinuity (no _LO dword for 890d) 00000000 RB_MRT_FLAG_BUFFER[0x3].ADDR_HI: 0 00000000 RB_MRT_FLAG_BUFFER[0x3].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 RB_SAMPLE_COUNT_ADDR: 0 - 00000000 RB_SAMPLE_COUNT_ADDR_HI: 0 00000000 0x8bf0: 00000000 00000000 0x8bf1: 00000000 00000000 0x8c02: 00000000 @@ -6187,10 +6106,8 @@ clusters: 00000000 0x8c15: 00000000 00000000 0x8c16: 00000000 00000000 RB_2D_DST_FLAGS: 0 - 00000000 RB_2D_DST_FLAGS_HI: 0 00000000 RB_2D_DST_FLAGS_PITCH: 0 00000000 RB_2D_DST_FLAGS_PLANE: 0 - 00000000 RB_2D_DST_FLAGS_PLANE_HI: 0 00000000 RB_2D_DST_FLAGS_PLANE_PITCH: 0 - cluster-name: CLUSTER_PS - context: 0 @@ -6218,35 +6135,26 @@ clusters: 00000000 VPC_VAR[0x3].DISABLE: 0 00000000 VPC_SO_CNTL: { ADDR = 0 } 00000000 VPC_SO_STREAM_COUNTS: 0 - 00000000 VPC_SO_STREAM_COUNTS_HI: 0 00000000 VPC_SO[0].BUFFER_BASE: 0 - 00000000 VPC_SO[0].BUFFER_BASE_HI: 0 00000000 VPC_SO[0].BUFFER_SIZE: 0 00000001 VPC_SO[0].BUFFER_STRIDE: 0x4 00000000 VPC_SO[0].BUFFER_OFFSET: 0 00000000 VPC_SO[0].FLUSH_BASE: 0 - 00000000 VPC_SO[0].FLUSH_BASE_HI: 0 00000000 VPC_SO[0x1].BUFFER_BASE: 0 - 00000000 VPC_SO[0x1].BUFFER_BASE_HI: 0 00000000 VPC_SO[0x1].BUFFER_SIZE: 0 00000001 VPC_SO[0x1].BUFFER_STRIDE: 0x4 00000000 VPC_SO[0x1].BUFFER_OFFSET: 0 00000000 VPC_SO[0x1].FLUSH_BASE: 0 - 00000000 VPC_SO[0x1].FLUSH_BASE_HI: 0 00000000 VPC_SO[0x2].BUFFER_BASE: 0 - 00000000 VPC_SO[0x2].BUFFER_BASE_HI: 0 00000000 VPC_SO[0x2].BUFFER_SIZE: 0 00000001 VPC_SO[0x2].BUFFER_STRIDE: 0x4 00000000 VPC_SO[0x2].BUFFER_OFFSET: 0 00000000 VPC_SO[0x2].FLUSH_BASE: 0 - 00000000 VPC_SO[0x2].FLUSH_BASE_HI: 0 00000000 VPC_SO[0x3].BUFFER_BASE: 0 - 00000000 VPC_SO[0x3].BUFFER_BASE_HI: 0 00000000 VPC_SO[0x3].BUFFER_SIZE: 0 00000001 VPC_SO[0x3].BUFFER_STRIDE: 0x4 00000000 VPC_SO[0x3].BUFFER_OFFSET: 0 00000000 VPC_SO[0x3].FLUSH_BASE: 0 - 00000000 VPC_SO[0x3].FLUSH_BASE_HI: 0 00000000 VPC_POINT_COORD_INVERT: { 0 } 00000000 VPC_UNKNOWN_9300: 0 00ff0001 VPC_VS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } @@ -6280,35 +6188,26 @@ clusters: 00000000 VPC_VAR[0x3].DISABLE: 0 00000000 VPC_SO_CNTL: { ADDR = 0 } 00000000 VPC_SO_STREAM_COUNTS: 0 - 00000000 VPC_SO_STREAM_COUNTS_HI: 0 00000000 VPC_SO[0].BUFFER_BASE: 0 - 00000000 VPC_SO[0].BUFFER_BASE_HI: 0 00000000 VPC_SO[0].BUFFER_SIZE: 0 00000001 VPC_SO[0].BUFFER_STRIDE: 0x4 00000000 VPC_SO[0].BUFFER_OFFSET: 0 00000000 VPC_SO[0].FLUSH_BASE: 0 - 00000000 VPC_SO[0].FLUSH_BASE_HI: 0 00000000 VPC_SO[0x1].BUFFER_BASE: 0 - 00000000 VPC_SO[0x1].BUFFER_BASE_HI: 0 00000000 VPC_SO[0x1].BUFFER_SIZE: 0 00000001 VPC_SO[0x1].BUFFER_STRIDE: 0x4 00000000 VPC_SO[0x1].BUFFER_OFFSET: 0 00000000 VPC_SO[0x1].FLUSH_BASE: 0 - 00000000 VPC_SO[0x1].FLUSH_BASE_HI: 0 00000000 VPC_SO[0x2].BUFFER_BASE: 0 - 00000000 VPC_SO[0x2].BUFFER_BASE_HI: 0 00000000 VPC_SO[0x2].BUFFER_SIZE: 0 00000001 VPC_SO[0x2].BUFFER_STRIDE: 0x4 00000000 VPC_SO[0x2].BUFFER_OFFSET: 0 00000000 VPC_SO[0x2].FLUSH_BASE: 0 - 00000000 VPC_SO[0x2].FLUSH_BASE_HI: 0 00000000 VPC_SO[0x3].BUFFER_BASE: 0 - 00000000 VPC_SO[0x3].BUFFER_BASE_HI: 0 00000000 VPC_SO[0x3].BUFFER_SIZE: 0 00000001 VPC_SO[0x3].BUFFER_STRIDE: 0x4 00000000 VPC_SO[0x3].BUFFER_OFFSET: 0 00000000 VPC_SO[0x3].FLUSH_BASE: 0 - 00000000 VPC_SO[0x3].FLUSH_BASE_HI: 0 00000000 VPC_POINT_COORD_INVERT: { 0 } 00000000 VPC_UNKNOWN_9300: 0 00ff0001 VPC_VS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } @@ -6353,132 +6252,100 @@ clusters: 00000000 VFD_ADD_OFFSET: { 0 } 00000000 VFD_INDEX_OFFSET: 0 00000000 VFD_INSTANCE_START_OFFSET: 0 - 1618e045 VFD_FETCH[0].BASE: 0x1618e045 - 00005505 VFD_FETCH[0].BASE_HI: 0x5505 + 55051618e045 VFD_FETCH[0].BASE: 0x55051618e045 00840800 VFD_FETCH[0].SIZE: 8652800 00000051 VFD_FETCH[0].STRIDE: 81 - 01100401 VFD_FETCH[0x1].BASE: 0x1100401 - 00000040 VFD_FETCH[0x1].BASE_HI: 0x40 + 4001100401 VFD_FETCH[0x1].BASE: 0x4001100401 04010402 VFD_FETCH[0x1].SIZE: 67175426 00000000 VFD_FETCH[0x1].STRIDE: 0 - 40080120 VFD_FETCH[0x2].BASE: 0x40080120 - 00004000 VFD_FETCH[0x2].BASE_HI: 0x4000 + 400040080120 VFD_FETCH[0x2].BASE: 0x400040080120 00140100 VFD_FETCH[0x2].SIZE: 1310976 00000002 VFD_FETCH[0x2].STRIDE: 2 - 00001090 VFD_FETCH[0x3].BASE: 0x1090 - 00000200 VFD_FETCH[0x3].BASE_HI: 0x200 + 20000001090 VFD_FETCH[0x3].BASE: 0x20000001090 11040100 VFD_FETCH[0x3].SIZE: 285475072 00000000 VFD_FETCH[0x3].STRIDE: 0 - 04000900 VFD_FETCH[0x4].BASE: 0x4000900 - 00000451 VFD_FETCH[0x4].BASE_HI: 0x451 + 45104000900 VFD_FETCH[0x4].BASE: 0x45104000900 01000806 VFD_FETCH[0x4].SIZE: 16779270 00000201 VFD_FETCH[0x4].STRIDE: 513 00004004 VFD_FETCH[0x5].BASE: 0x4004 - 00000000 VFD_FETCH[0x5].BASE_HI: 0 00000080 VFD_FETCH[0x5].SIZE: 128 00000000 VFD_FETCH[0x5].STRIDE: 0 - 14008030 VFD_FETCH[0x6].BASE: 0x14008030 - 0000e303 VFD_FETCH[0x6].BASE_HI: 0xe303 + e30314008030 VFD_FETCH[0x6].BASE: 0xe30314008030 10020400 VFD_FETCH[0x6].SIZE: 268567552 00000088 VFD_FETCH[0x6].STRIDE: 136 - 02000030 VFD_FETCH[0x7].BASE: 0x2000030 - 00001140 VFD_FETCH[0x7].BASE_HI: 0x1140 + 114002000030 VFD_FETCH[0x7].BASE: 0x114002000030 40400000 VFD_FETCH[0x7].SIZE: 1077936128 00000041 VFD_FETCH[0x7].STRIDE: 65 - c0100100 VFD_FETCH[0x8].BASE: 0xc0100100 - 00001244 VFD_FETCH[0x8].BASE_HI: 0x1244 + 1244c0100100 VFD_FETCH[0x8].BASE: 0x1244c0100100 00050004 VFD_FETCH[0x8].SIZE: 327684 00000040 VFD_FETCH[0x8].STRIDE: 64 00044000 VFD_FETCH[0x9].BASE: 0x44000 - 00000000 VFD_FETCH[0x9].BASE_HI: 0 80000020 VFD_FETCH[0x9].SIZE: 2147483680 00000008 VFD_FETCH[0x9].STRIDE: 8 - 10006004 VFD_FETCH[0xa].BASE: 0x10006004 - 0000222a VFD_FETCH[0xa].BASE_HI: 0x222a + 222a10006004 VFD_FETCH[0xa].BASE: 0x222a10006004 02042020 VFD_FETCH[0xa].SIZE: 33824800 00000681 VFD_FETCH[0xa].STRIDE: 1665 - 02101020 VFD_FETCH[0xb].BASE: 0x2101020 - 00000080 VFD_FETCH[0xb].BASE_HI: 0x80 + 8002101020 VFD_FETCH[0xb].BASE: 0x8002101020 00040020 VFD_FETCH[0xb].SIZE: 262176 00000050 VFD_FETCH[0xb].STRIDE: 80 - 0a436062 VFD_FETCH[0xc].BASE: 0xa436062 - 00003041 VFD_FETCH[0xc].BASE_HI: 0x3041 + 30410a436062 VFD_FETCH[0xc].BASE: 0x30410a436062 06102040 VFD_FETCH[0xc].SIZE: 101720128 00000200 VFD_FETCH[0xc].STRIDE: 512 00800864 VFD_FETCH[0xd].BASE: 0x800864 - 00000000 VFD_FETCH[0xd].BASE_HI: 0 10400044 VFD_FETCH[0xd].SIZE: 272629828 00000010 VFD_FETCH[0xd].STRIDE: 16 - 061b8c2a VFD_FETCH[0xe].BASE: 0x61b8c2a - 00000004 VFD_FETCH[0xe].BASE_HI: 0x4 + 4061b8c2a VFD_FETCH[0xe].BASE: 0x4061b8c2a 01004391 VFD_FETCH[0xe].SIZE: 16794513 00000440 VFD_FETCH[0xe].STRIDE: 1088 - 02000000 VFD_FETCH[0xf].BASE: 0x2000000 - 00000200 VFD_FETCH[0xf].BASE_HI: 0x200 + 20002000000 VFD_FETCH[0xf].BASE: 0x20002000000 41250000 VFD_FETCH[0xf].SIZE: 1092943872 00000010 VFD_FETCH[0xf].STRIDE: 16 - 01443027 VFD_FETCH[0x10].BASE: 0x1443027 - 00001000 VFD_FETCH[0x10].BASE_HI: 0x1000 + 100001443027 VFD_FETCH[0x10].BASE: 0x100001443027 c1100240 VFD_FETCH[0x10].SIZE: 3239051840 00000002 VFD_FETCH[0x10].STRIDE: 2 - 0000b404 VFD_FETCH[0x11].BASE: 0xb404 - 00000080 VFD_FETCH[0x11].BASE_HI: 0x80 + 800000b404 VFD_FETCH[0x11].BASE: 0x800000b404 12404000 VFD_FETCH[0x11].SIZE: 306200576 00000280 VFD_FETCH[0x11].STRIDE: 640 - 8100011c VFD_FETCH[0x12].BASE: 0x8100011c - 00000218 VFD_FETCH[0x12].BASE_HI: 0x218 + 2188100011c VFD_FETCH[0x12].BASE: 0x2188100011c 0050b000 VFD_FETCH[0x12].SIZE: 5287936 00000462 VFD_FETCH[0x12].STRIDE: 1122 - 00004001 VFD_FETCH[0x13].BASE: 0x4001 - 0000000c VFD_FETCH[0x13].BASE_HI: 0xc + c00004001 VFD_FETCH[0x13].BASE: 0xc00004001 00810880 VFD_FETCH[0x13].SIZE: 8456320 00000000 VFD_FETCH[0x13].STRIDE: 0 - 00025022 VFD_FETCH[0x14].BASE: 0x25022 - 00000040 VFD_FETCH[0x14].BASE_HI: 0x40 + 4000025022 VFD_FETCH[0x14].BASE: 0x4000025022 015c1040 VFD_FETCH[0x14].SIZE: 22810688 00000000 VFD_FETCH[0x14].STRIDE: 0 7a540120 VFD_FETCH[0x15].BASE: 0x7a540120 - 00000000 VFD_FETCH[0x15].BASE_HI: 0 02800306 VFD_FETCH[0x15].SIZE: 41943814 00000024 VFD_FETCH[0x15].STRIDE: 36 - 00040f13 VFD_FETCH[0x16].BASE: 0x40f13 - 00000850 VFD_FETCH[0x16].BASE_HI: 0x850 + 85000040f13 VFD_FETCH[0x16].BASE: 0x85000040f13 00425010 VFD_FETCH[0x16].SIZE: 4345872 00000408 VFD_FETCH[0x16].STRIDE: 1032 - 04012000 VFD_FETCH[0x17].BASE: 0x4012000 - 00004111 VFD_FETCH[0x17].BASE_HI: 0x4111 + 411104012000 VFD_FETCH[0x17].BASE: 0x411104012000 08012800 VFD_FETCH[0x17].SIZE: 134293504 00000000 VFD_FETCH[0x17].STRIDE: 0 00022003 VFD_FETCH[0x18].BASE: 0x22003 - 00000000 VFD_FETCH[0x18].BASE_HI: 0 504228ac VFD_FETCH[0x18].SIZE: 1346513068 00000300 VFD_FETCH[0x18].STRIDE: 768 - 40a40080 VFD_FETCH[0x19].BASE: 0x40a40080 - 0000c010 VFD_FETCH[0x19].BASE_HI: 0xc010 + c01040a40080 VFD_FETCH[0x19].BASE: 0xc01040a40080 00002000 VFD_FETCH[0x19].SIZE: 8192 00000101 VFD_FETCH[0x19].STRIDE: 257 - 88248411 VFD_FETCH[0x1a].BASE: 0x88248411 - 00000400 VFD_FETCH[0x1a].BASE_HI: 0x400 + 40088248411 VFD_FETCH[0x1a].BASE: 0x40088248411 2604c030 VFD_FETCH[0x1a].SIZE: 637845552 00000020 VFD_FETCH[0x1a].STRIDE: 32 - 00000000 VFD_FETCH[0x1b].BASE: 0 - 00000924 VFD_FETCH[0x1b].BASE_HI: 0x924 + 92400000000 VFD_FETCH[0x1b].BASE: 0x92400000000 00100000 VFD_FETCH[0x1b].SIZE: 1048576 00000000 VFD_FETCH[0x1b].STRIDE: 0 - 048c1100 VFD_FETCH[0x1c].BASE: 0x48c1100 - 00000b06 VFD_FETCH[0x1c].BASE_HI: 0xb06 + b06048c1100 VFD_FETCH[0x1c].BASE: 0xb06048c1100 00007264 VFD_FETCH[0x1c].SIZE: 29284 00000c11 VFD_FETCH[0x1c].STRIDE: 3089 - 00000120 VFD_FETCH[0x1d].BASE: 0x120 - 00004547 VFD_FETCH[0x1d].BASE_HI: 0x4547 + 454700000120 VFD_FETCH[0x1d].BASE: 0x454700000120 46000080 VFD_FETCH[0x1d].SIZE: 1174405248 00000100 VFD_FETCH[0x1d].STRIDE: 256 - 001a026c VFD_FETCH[0x1e].BASE: 0x1a026c - 00000545 VFD_FETCH[0x1e].BASE_HI: 0x545 + 545001a026c VFD_FETCH[0x1e].BASE: 0x545001a026c 22500060 VFD_FETCH[0x1e].SIZE: 575668320 00000002 VFD_FETCH[0x1e].STRIDE: 2 - 00041100 VFD_FETCH[0x1f].BASE: 0x41100 - 00001100 VFD_FETCH[0x1f].BASE_HI: 0x1100 + 110000041100 VFD_FETCH[0x1f].BASE: 0x110000041100 01810080 VFD_FETCH[0x1f].SIZE: 25231488 00000020 VFD_FETCH[0x1f].STRIDE: 32 00002320 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0x119 | FORMAT = 0 | SWAP = WZYX } @@ -6613,132 +6480,100 @@ clusters: 00000000 VFD_ADD_OFFSET: { 0 } 00000000 VFD_INDEX_OFFSET: 0 00000000 VFD_INSTANCE_START_OFFSET: 0 - 1618e045 VFD_FETCH[0].BASE: 0x1618e045 - 00005505 VFD_FETCH[0].BASE_HI: 0x5505 + 55051618e045 VFD_FETCH[0].BASE: 0x55051618e045 00840800 VFD_FETCH[0].SIZE: 8652800 00000051 VFD_FETCH[0].STRIDE: 81 - 01100401 VFD_FETCH[0x1].BASE: 0x1100401 - 00000040 VFD_FETCH[0x1].BASE_HI: 0x40 + 4001100401 VFD_FETCH[0x1].BASE: 0x4001100401 04010402 VFD_FETCH[0x1].SIZE: 67175426 00000000 VFD_FETCH[0x1].STRIDE: 0 - 40080120 VFD_FETCH[0x2].BASE: 0x40080120 - 00004000 VFD_FETCH[0x2].BASE_HI: 0x4000 + 400040080120 VFD_FETCH[0x2].BASE: 0x400040080120 00140100 VFD_FETCH[0x2].SIZE: 1310976 00000002 VFD_FETCH[0x2].STRIDE: 2 - 00001090 VFD_FETCH[0x3].BASE: 0x1090 - 00000200 VFD_FETCH[0x3].BASE_HI: 0x200 + 20000001090 VFD_FETCH[0x3].BASE: 0x20000001090 11040100 VFD_FETCH[0x3].SIZE: 285475072 00000000 VFD_FETCH[0x3].STRIDE: 0 - 04000900 VFD_FETCH[0x4].BASE: 0x4000900 - 00000451 VFD_FETCH[0x4].BASE_HI: 0x451 + 45104000900 VFD_FETCH[0x4].BASE: 0x45104000900 01000806 VFD_FETCH[0x4].SIZE: 16779270 00000201 VFD_FETCH[0x4].STRIDE: 513 00004004 VFD_FETCH[0x5].BASE: 0x4004 - 00000000 VFD_FETCH[0x5].BASE_HI: 0 00000080 VFD_FETCH[0x5].SIZE: 128 00000000 VFD_FETCH[0x5].STRIDE: 0 - 14008030 VFD_FETCH[0x6].BASE: 0x14008030 - 0000e303 VFD_FETCH[0x6].BASE_HI: 0xe303 + e30314008030 VFD_FETCH[0x6].BASE: 0xe30314008030 10020400 VFD_FETCH[0x6].SIZE: 268567552 00000088 VFD_FETCH[0x6].STRIDE: 136 - 02000030 VFD_FETCH[0x7].BASE: 0x2000030 - 00001140 VFD_FETCH[0x7].BASE_HI: 0x1140 + 114002000030 VFD_FETCH[0x7].BASE: 0x114002000030 40400000 VFD_FETCH[0x7].SIZE: 1077936128 00000041 VFD_FETCH[0x7].STRIDE: 65 - c0100100 VFD_FETCH[0x8].BASE: 0xc0100100 - 00001244 VFD_FETCH[0x8].BASE_HI: 0x1244 + 1244c0100100 VFD_FETCH[0x8].BASE: 0x1244c0100100 00050004 VFD_FETCH[0x8].SIZE: 327684 00000040 VFD_FETCH[0x8].STRIDE: 64 00044000 VFD_FETCH[0x9].BASE: 0x44000 - 00000000 VFD_FETCH[0x9].BASE_HI: 0 80000020 VFD_FETCH[0x9].SIZE: 2147483680 00000008 VFD_FETCH[0x9].STRIDE: 8 - 10006004 VFD_FETCH[0xa].BASE: 0x10006004 - 0000222a VFD_FETCH[0xa].BASE_HI: 0x222a + 222a10006004 VFD_FETCH[0xa].BASE: 0x222a10006004 02042020 VFD_FETCH[0xa].SIZE: 33824800 00000681 VFD_FETCH[0xa].STRIDE: 1665 - 02101020 VFD_FETCH[0xb].BASE: 0x2101020 - 00000080 VFD_FETCH[0xb].BASE_HI: 0x80 + 8002101020 VFD_FETCH[0xb].BASE: 0x8002101020 00040020 VFD_FETCH[0xb].SIZE: 262176 00000050 VFD_FETCH[0xb].STRIDE: 80 - 0a436062 VFD_FETCH[0xc].BASE: 0xa436062 - 00003041 VFD_FETCH[0xc].BASE_HI: 0x3041 + 30410a436062 VFD_FETCH[0xc].BASE: 0x30410a436062 06102040 VFD_FETCH[0xc].SIZE: 101720128 00000200 VFD_FETCH[0xc].STRIDE: 512 00800864 VFD_FETCH[0xd].BASE: 0x800864 - 00000000 VFD_FETCH[0xd].BASE_HI: 0 10400044 VFD_FETCH[0xd].SIZE: 272629828 00000010 VFD_FETCH[0xd].STRIDE: 16 - 061b8c2a VFD_FETCH[0xe].BASE: 0x61b8c2a - 00000004 VFD_FETCH[0xe].BASE_HI: 0x4 + 4061b8c2a VFD_FETCH[0xe].BASE: 0x4061b8c2a 01004391 VFD_FETCH[0xe].SIZE: 16794513 00000440 VFD_FETCH[0xe].STRIDE: 1088 - 02000000 VFD_FETCH[0xf].BASE: 0x2000000 - 00000200 VFD_FETCH[0xf].BASE_HI: 0x200 + 20002000000 VFD_FETCH[0xf].BASE: 0x20002000000 41250000 VFD_FETCH[0xf].SIZE: 1092943872 00000010 VFD_FETCH[0xf].STRIDE: 16 - 01443027 VFD_FETCH[0x10].BASE: 0x1443027 - 00001000 VFD_FETCH[0x10].BASE_HI: 0x1000 + 100001443027 VFD_FETCH[0x10].BASE: 0x100001443027 c1100240 VFD_FETCH[0x10].SIZE: 3239051840 00000002 VFD_FETCH[0x10].STRIDE: 2 - 0000b404 VFD_FETCH[0x11].BASE: 0xb404 - 00000080 VFD_FETCH[0x11].BASE_HI: 0x80 + 800000b404 VFD_FETCH[0x11].BASE: 0x800000b404 12404000 VFD_FETCH[0x11].SIZE: 306200576 00000280 VFD_FETCH[0x11].STRIDE: 640 - 8100011c VFD_FETCH[0x12].BASE: 0x8100011c - 00000218 VFD_FETCH[0x12].BASE_HI: 0x218 + 2188100011c VFD_FETCH[0x12].BASE: 0x2188100011c 0050b000 VFD_FETCH[0x12].SIZE: 5287936 00000462 VFD_FETCH[0x12].STRIDE: 1122 - 00004001 VFD_FETCH[0x13].BASE: 0x4001 - 0000000c VFD_FETCH[0x13].BASE_HI: 0xc + c00004001 VFD_FETCH[0x13].BASE: 0xc00004001 00810880 VFD_FETCH[0x13].SIZE: 8456320 00000000 VFD_FETCH[0x13].STRIDE: 0 - 00025022 VFD_FETCH[0x14].BASE: 0x25022 - 00000040 VFD_FETCH[0x14].BASE_HI: 0x40 + 4000025022 VFD_FETCH[0x14].BASE: 0x4000025022 015c1040 VFD_FETCH[0x14].SIZE: 22810688 00000000 VFD_FETCH[0x14].STRIDE: 0 7a540120 VFD_FETCH[0x15].BASE: 0x7a540120 - 00000000 VFD_FETCH[0x15].BASE_HI: 0 02800306 VFD_FETCH[0x15].SIZE: 41943814 00000024 VFD_FETCH[0x15].STRIDE: 36 - 00040f13 VFD_FETCH[0x16].BASE: 0x40f13 - 00000850 VFD_FETCH[0x16].BASE_HI: 0x850 + 85000040f13 VFD_FETCH[0x16].BASE: 0x85000040f13 00425010 VFD_FETCH[0x16].SIZE: 4345872 00000408 VFD_FETCH[0x16].STRIDE: 1032 - 04012000 VFD_FETCH[0x17].BASE: 0x4012000 - 00004111 VFD_FETCH[0x17].BASE_HI: 0x4111 + 411104012000 VFD_FETCH[0x17].BASE: 0x411104012000 08012800 VFD_FETCH[0x17].SIZE: 134293504 00000000 VFD_FETCH[0x17].STRIDE: 0 00022003 VFD_FETCH[0x18].BASE: 0x22003 - 00000000 VFD_FETCH[0x18].BASE_HI: 0 504228ac VFD_FETCH[0x18].SIZE: 1346513068 00000300 VFD_FETCH[0x18].STRIDE: 768 - 40a40080 VFD_FETCH[0x19].BASE: 0x40a40080 - 0000c010 VFD_FETCH[0x19].BASE_HI: 0xc010 + c01040a40080 VFD_FETCH[0x19].BASE: 0xc01040a40080 00002000 VFD_FETCH[0x19].SIZE: 8192 00000101 VFD_FETCH[0x19].STRIDE: 257 - 88248411 VFD_FETCH[0x1a].BASE: 0x88248411 - 00000400 VFD_FETCH[0x1a].BASE_HI: 0x400 + 40088248411 VFD_FETCH[0x1a].BASE: 0x40088248411 2604c030 VFD_FETCH[0x1a].SIZE: 637845552 00000020 VFD_FETCH[0x1a].STRIDE: 32 - 00000000 VFD_FETCH[0x1b].BASE: 0 - 00000924 VFD_FETCH[0x1b].BASE_HI: 0x924 + 92400000000 VFD_FETCH[0x1b].BASE: 0x92400000000 00100000 VFD_FETCH[0x1b].SIZE: 1048576 00000000 VFD_FETCH[0x1b].STRIDE: 0 - 048c1100 VFD_FETCH[0x1c].BASE: 0x48c1100 - 00000b06 VFD_FETCH[0x1c].BASE_HI: 0xb06 + b06048c1100 VFD_FETCH[0x1c].BASE: 0xb06048c1100 00007264 VFD_FETCH[0x1c].SIZE: 29284 00000c11 VFD_FETCH[0x1c].STRIDE: 3089 - 00000120 VFD_FETCH[0x1d].BASE: 0x120 - 00004547 VFD_FETCH[0x1d].BASE_HI: 0x4547 + 454700000120 VFD_FETCH[0x1d].BASE: 0x454700000120 46000080 VFD_FETCH[0x1d].SIZE: 1174405248 00000100 VFD_FETCH[0x1d].STRIDE: 256 - 001a026c VFD_FETCH[0x1e].BASE: 0x1a026c - 00000545 VFD_FETCH[0x1e].BASE_HI: 0x545 + 545001a026c VFD_FETCH[0x1e].BASE: 0x545001a026c 22500060 VFD_FETCH[0x1e].SIZE: 575668320 00000002 VFD_FETCH[0x1e].STRIDE: 2 - 00041100 VFD_FETCH[0x1f].BASE: 0x41100 - 00001100 VFD_FETCH[0x1f].BASE_HI: 0x1100 + 110000041100 VFD_FETCH[0x1f].BASE: 0x110000041100 01810080 VFD_FETCH[0x1f].SIZE: 25231488 00000020 VFD_FETCH[0x1f].STRIDE: 32 00002320 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0x119 | FORMAT = 0 | SWAP = WZYX } @@ -6901,7 +6736,6 @@ clusters: 00000100 HLSQ_GS_CNTL: { CONSTLEN = 0 | ENABLED } 40204000 HLSQ_LOAD_STATE_GEOM_CMD: 0x40204000 00000000 HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR: 0 - 00000000 HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR_HI: 0 - context: 1 00000140 HLSQ_VS_CNTL: { CONSTLEN = 256 | ENABLED } 00000000 HLSQ_HS_CNTL: { CONSTLEN = 0 } @@ -6909,7 +6743,6 @@ clusters: 00000100 HLSQ_GS_CNTL: { CONSTLEN = 0 | ENABLED } 40204000 HLSQ_LOAD_STATE_GEOM_CMD: 0x40204000 00000000 HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR: 0 - 00000000 HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR_HI: 0 - cluster-name: CLUSTER_SP_VS - context: 0 00000000 SP_VS_CTRL_REG0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 } @@ -6940,11 +6773,9 @@ clusters: 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00000000 SP_VS_OBJ_FIRST_EXEC_OFFSET: 0 - 8e5d7d37 SP_VS_OBJ_START: 0x8e5d7d37 - 0001fcd5 SP_VS_OBJ_START_HI: 0x1fcd5 + 1fcd58e5d7d37 SP_VS_OBJ_START: 0x1fcd58e5d7d37 00000000 SP_VS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 } 00000000 SP_VS_PVT_MEM_ADDR: 0 - 00000000 SP_VS_PVT_MEM_ADDR_HI: 0 00000000 SP_VS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 } 00000080 SP_VS_TEX_COUNT: 128 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } @@ -6953,11 +6784,9 @@ clusters: 00000000 SP_HS_WAVE_INPUT_SIZE: 0 00000000 SP_HS_BRANCH_COND: 0 00000000 SP_HS_OBJ_FIRST_EXEC_OFFSET: 0 - 780a8ca5 SP_HS_OBJ_START: 0x780a8ca5 - 0001aad2 SP_HS_OBJ_START_HI: 0x1aad2 + 1aad2780a8ca5 SP_HS_OBJ_START: 0x1aad2780a8ca5 00000000 SP_HS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 } 00000000 SP_HS_PVT_MEM_ADDR: 0 - 00000000 SP_HS_PVT_MEM_ADDR_HI: 0 00000000 SP_HS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 } 00000080 SP_HS_TEX_COUNT: 128 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } @@ -6990,11 +6819,9 @@ clusters: 00000000 SP_DS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00000000 SP_DS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00000000 SP_DS_OBJ_FIRST_EXEC_OFFSET: 0 - 7abf500d SP_DS_OBJ_START: 0x7abf500d - 00017e52 SP_DS_OBJ_START_HI: 0x17e52 + 17e527abf500d SP_DS_OBJ_START: 0x17e527abf500d 00000000 SP_DS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 } 00000000 SP_DS_PVT_MEM_ADDR: 0 - 00000000 SP_DS_PVT_MEM_ADDR_HI: 0 00000000 SP_DS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 } 00000080 SP_DS_TEX_COUNT: 128 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } @@ -7028,31 +6855,21 @@ clusters: 00000000 SP_GS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00000000 SP_GS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00000000 SP_GS_OBJ_FIRST_EXEC_OFFSET: 0 - 14e2046b SP_GS_OBJ_START: 0x14e2046b - 00004c8f SP_GS_OBJ_START_HI: 0x4c8f + 4c8f14e2046b SP_GS_OBJ_START: 0x4c8f14e2046b 00000000 SP_GS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 } 00000000 SP_GS_PVT_MEM_ADDR: 0 - 00000000 SP_GS_PVT_MEM_ADDR_HI: 0 00000000 SP_GS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 } 00000080 SP_GS_TEX_COUNT: 128 00000100 SP_GS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } 00000000 SP_GS_INSTRLEN: 0 - e0c4d9c6 SP_VS_TEX_SAMP: 0xe0c4d9c6 - 0000ed21 SP_VS_TEX_SAMP_HI: 0xed21 - 73a9bba1 SP_HS_TEX_SAMP: 0x73a9bba1 - 00001a05 SP_HS_TEX_SAMP_HI: 0x1a05 - b21263a4 SP_DS_TEX_SAMP: 0xb21263a4 - 0001a6b5 SP_DS_TEX_SAMP_HI: 0x1a6b5 - ee7b37d3 SP_GS_TEX_SAMP: 0xee7b37d3 - 000047fc SP_GS_TEX_SAMP_HI: 0x47fc - 5eb05388 SP_VS_TEX_CONST: 0x5eb05388 - 0001f31d SP_VS_TEX_CONST_HI: 0x1f31d - 90f84815 SP_HS_TEX_CONST: 0x90f84815 - 00018461 SP_HS_TEX_CONST_HI: 0x18461 - 96f329d4 SP_DS_TEX_CONST: 0x96f329d4 - 00015905 SP_DS_TEX_CONST_HI: 0x15905 - e6ce68a3 SP_GS_TEX_CONST: 0xe6ce68a3 - 00007a12 SP_GS_TEX_CONST_HI: 0x7a12 + ed21e0c4d9c6 SP_VS_TEX_SAMP: 0xed21e0c4d9c6 + 1a0573a9bba1 SP_HS_TEX_SAMP: 0x1a0573a9bba1 + 1a6b5b21263a4 SP_DS_TEX_SAMP: 0x1a6b5b21263a4 + 47fcee7b37d3 SP_GS_TEX_SAMP: 0x47fcee7b37d3 + 1f31d5eb05388 SP_VS_TEX_CONST: 0x1f31d5eb05388 + 1846190f84815 SP_HS_TEX_CONST: 0x1846190f84815 + 1590596f329d4 SP_DS_TEX_CONST: 0x1590596f329d4 + 7a12e6ce68a3 SP_GS_TEX_CONST: 0x7a12e6ce68a3 00000000 0xa8c0: 00000000 00000000 0xa8c1: 00000000 00000000 0xa8c2: 00000000 @@ -7086,11 +6903,9 @@ clusters: 00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00000000 SP_VS_OBJ_FIRST_EXEC_OFFSET: 0 - 8e5d7d37 SP_VS_OBJ_START: 0x8e5d7d37 - 0001fcd5 SP_VS_OBJ_START_HI: 0x1fcd5 + 1fcd58e5d7d37 SP_VS_OBJ_START: 0x1fcd58e5d7d37 00000000 SP_VS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 } 00000000 SP_VS_PVT_MEM_ADDR: 0 - 00000000 SP_VS_PVT_MEM_ADDR_HI: 0 00000000 SP_VS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 } 00000080 SP_VS_TEX_COUNT: 128 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } @@ -7099,11 +6914,9 @@ clusters: 00000000 SP_HS_WAVE_INPUT_SIZE: 0 00000000 SP_HS_BRANCH_COND: 0 00000000 SP_HS_OBJ_FIRST_EXEC_OFFSET: 0 - 780a8ca5 SP_HS_OBJ_START: 0x780a8ca5 - 0001aad2 SP_HS_OBJ_START_HI: 0x1aad2 + 1aad2780a8ca5 SP_HS_OBJ_START: 0x1aad2780a8ca5 00000000 SP_HS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 } 00000000 SP_HS_PVT_MEM_ADDR: 0 - 00000000 SP_HS_PVT_MEM_ADDR_HI: 0 00000000 SP_HS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 } 00000080 SP_HS_TEX_COUNT: 128 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } @@ -7136,11 +6949,9 @@ clusters: 00000000 SP_DS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00000000 SP_DS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00000000 SP_DS_OBJ_FIRST_EXEC_OFFSET: 0 - 7abf500d SP_DS_OBJ_START: 0x7abf500d - 00017e52 SP_DS_OBJ_START_HI: 0x17e52 + 17e527abf500d SP_DS_OBJ_START: 0x17e527abf500d 00000000 SP_DS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 } 00000000 SP_DS_PVT_MEM_ADDR: 0 - 00000000 SP_DS_PVT_MEM_ADDR_HI: 0 00000000 SP_DS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 } 00000080 SP_DS_TEX_COUNT: 128 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 } @@ -7174,31 +6985,21 @@ clusters: 00000000 SP_GS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00000000 SP_GS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 } 00000000 SP_GS_OBJ_FIRST_EXEC_OFFSET: 0 - 14e2046b SP_GS_OBJ_START: 0x14e2046b - 00004c8f SP_GS_OBJ_START_HI: 0x4c8f + 4c8f14e2046b SP_GS_OBJ_START: 0x4c8f14e2046b 00000000 SP_GS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 } 00000000 SP_GS_PVT_MEM_ADDR: 0 - 00000000 SP_GS_PVT_MEM_ADDR_HI: 0 00000000 SP_GS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 } 00000080 SP_GS_TEX_COUNT: 128 00000100 SP_GS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } 00000000 SP_GS_INSTRLEN: 0 - e0c4d9c6 SP_VS_TEX_SAMP: 0xe0c4d9c6 - 0000ed21 SP_VS_TEX_SAMP_HI: 0xed21 - 73a9bba1 SP_HS_TEX_SAMP: 0x73a9bba1 - 00001a05 SP_HS_TEX_SAMP_HI: 0x1a05 - b21263a4 SP_DS_TEX_SAMP: 0xb21263a4 - 0001a6b5 SP_DS_TEX_SAMP_HI: 0x1a6b5 - ee7b37d3 SP_GS_TEX_SAMP: 0xee7b37d3 - 000047fc SP_GS_TEX_SAMP_HI: 0x47fc - 5eb05388 SP_VS_TEX_CONST: 0x5eb05388 - 0001f31d SP_VS_TEX_CONST_HI: 0x1f31d - 90f84815 SP_HS_TEX_CONST: 0x90f84815 - 00018461 SP_HS_TEX_CONST_HI: 0x18461 - 96f329d4 SP_DS_TEX_CONST: 0x96f329d4 - 00015905 SP_DS_TEX_CONST_HI: 0x15905 - e6ce68a3 SP_GS_TEX_CONST: 0xe6ce68a3 - 00007a12 SP_GS_TEX_CONST_HI: 0x7a12 + ed21e0c4d9c6 SP_VS_TEX_SAMP: 0xed21e0c4d9c6 + 1a0573a9bba1 SP_HS_TEX_SAMP: 0x1a0573a9bba1 + 1a6b5b21263a4 SP_DS_TEX_SAMP: 0x1a6b5b21263a4 + 47fcee7b37d3 SP_GS_TEX_SAMP: 0x47fcee7b37d3 + 1f31d5eb05388 SP_VS_TEX_CONST: 0x1f31d5eb05388 + 1846190f84815 SP_HS_TEX_CONST: 0x1846190f84815 + 1590596f329d4 SP_DS_TEX_CONST: 0x1590596f329d4 + 7a12e6ce68a3 SP_GS_TEX_CONST: 0x7a12e6ce68a3 00000000 0xa8c0: 00000000 00000000 0xa8c1: 00000000 00000000 0xa8c2: 00000000 @@ -7208,28 +7009,18 @@ clusters: 00000140 HLSQ_FS_CNTL: { CONSTLEN = 256 | ENABLED } 00000000 HLSQ_SHARED_CONSTS: { 0 } 00000000 HLSQ_BINDLESS_BASE[0].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0].ADDR_HI: 0 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR_HI: 0 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR_HI: 0 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR_HI: 0 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR_HI: 0 - context: 1 00000140 HLSQ_FS_CNTL: { CONSTLEN = 256 | ENABLED } 00000000 HLSQ_SHARED_CONSTS: { 0 } 00000000 HLSQ_BINDLESS_BASE[0].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0].ADDR_HI: 0 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR_HI: 0 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR_HI: 0 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR_HI: 0 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR_HI: 0 - cluster-name: CLUSTER_SP_VS - context: 0 deadbeef HLSQ_2D_EVENT_CMD: { STATE_ID = 0xbe | EVENT = 0x6f | 0xdead0080 } @@ -7240,42 +7031,29 @@ clusters: 00000000 SP_MODE_CONTROL: { ISAMMODE = 0 } 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } 00000000 SP_FS_INSTRLEN: 0 - 2764a40a SP_BINDLESS_BASE[0].ADDR: 0x2764a40a - 0000cd30 SP_BINDLESS_BASE[0].ADDR_HI: 0xcd30 - 93870830 SP_BINDLESS_BASE[0x1].ADDR: 0x93870830 - 00017dc4 SP_BINDLESS_BASE[0x1].ADDR_HI: 0x17dc4 - d3064206 SP_BINDLESS_BASE[0x2].ADDR: 0xd3064206 - 00014b45 SP_BINDLESS_BASE[0x2].ADDR_HI: 0x14b45 - bfafe9ba SP_BINDLESS_BASE[0x3].ADDR: 0xbfafe9ba - 0001ddc9 SP_BINDLESS_BASE[0x3].ADDR_HI: 0x1ddc9 - efda4292 SP_BINDLESS_BASE[0x4].ADDR: 0xefda4292 - 0000bd3b SP_BINDLESS_BASE[0x4].ADDR_HI: 0xbd3b - 0c0e0691 SP_IBO: 0xc0e0691 - 00013c40 SP_IBO_HI: 0x13c40 + cd302764a40a SP_BINDLESS_BASE[0].ADDR: 0xcd302764a40a + 17dc493870830 SP_BINDLESS_BASE[0x1].ADDR: 0x17dc493870830 + 14b45d3064206 SP_BINDLESS_BASE[0x2].ADDR: 0x14b45d3064206 + 1ddc9bfafe9ba SP_BINDLESS_BASE[0x3].ADDR: 0x1ddc9bfafe9ba + bd3befda4292 SP_BINDLESS_BASE[0x4].ADDR: 0xbd3befda4292 + 13c400c0e0691 SP_IBO: 0x13c400c0e0691 00000040 SP_IBO_COUNT: 64 - context: 1 00000000 SP_MODE_CONTROL: { ISAMMODE = 0 } 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } 00000000 SP_FS_INSTRLEN: 0 - 2764a40a SP_BINDLESS_BASE[0].ADDR: 0x2764a40a - 0000cd30 SP_BINDLESS_BASE[0].ADDR_HI: 0xcd30 - 93870830 SP_BINDLESS_BASE[0x1].ADDR: 0x93870830 - 00017dc4 SP_BINDLESS_BASE[0x1].ADDR_HI: 0x17dc4 - d3064206 SP_BINDLESS_BASE[0x2].ADDR: 0xd3064206 - 00014b45 SP_BINDLESS_BASE[0x2].ADDR_HI: 0x14b45 - bfafe9ba SP_BINDLESS_BASE[0x3].ADDR: 0xbfafe9ba - 0001ddc9 SP_BINDLESS_BASE[0x3].ADDR_HI: 0x1ddc9 - efda4292 SP_BINDLESS_BASE[0x4].ADDR: 0xefda4292 - 0000bd3b SP_BINDLESS_BASE[0x4].ADDR_HI: 0xbd3b - 0c0e0691 SP_IBO: 0xc0e0691 - 00013c40 SP_IBO_HI: 0x13c40 + cd302764a40a SP_BINDLESS_BASE[0].ADDR: 0xcd302764a40a + 17dc493870830 SP_BINDLESS_BASE[0x1].ADDR: 0x17dc493870830 + 14b45d3064206 SP_BINDLESS_BASE[0x2].ADDR: 0x14b45d3064206 + 1ddc9bfafe9ba SP_BINDLESS_BASE[0x3].ADDR: 0x1ddc9bfafe9ba + bd3befda4292 SP_BINDLESS_BASE[0x4].ADDR: 0xbd3befda4292 + 13c400c0e0691 SP_IBO: 0x13c400c0e0691 00000040 SP_IBO_COUNT: 64 - cluster-name: CLUSTER_SP_VS - context: 0 00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000000 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000000 SP_TP_BORDER_COLOR_BASE_ADDR: 0 - 00000000 SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0 00000000 SP_TP_SAMPLE_CONFIG: { 0 } 00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } 00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } @@ -7288,7 +7066,6 @@ clusters: 00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000000 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000000 SP_TP_BORDER_COLOR_BASE_ADDR: 0 - 00000000 SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0 00000000 SP_TP_SAMPLE_CONFIG: { 0 } 00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } 00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } @@ -7320,17 +7097,11 @@ clusters: 00000001 HLSQ_CS_KERNEL_GROUP_Z: 0x1 40304000 HLSQ_LOAD_STATE_FRAG_CMD: 0x40304000 8c415430 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR: 0x8c415430 - 00000000 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR_HI: 0 00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR: 0 - 00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR_HI: 0 00000000 HLSQ_CS_BINDLESS_BASE[0x1].ADDR: 0 - 00000000 HLSQ_CS_BINDLESS_BASE[0x1].ADDR_HI: 0 00000000 HLSQ_CS_BINDLESS_BASE[0x2].ADDR: 0 - 00000000 HLSQ_CS_BINDLESS_BASE[0x2].ADDR_HI: 0 00000000 HLSQ_CS_BINDLESS_BASE[0x3].ADDR: 0 - 00000000 HLSQ_CS_BINDLESS_BASE[0x3].ADDR_HI: 0 00000000 HLSQ_CS_BINDLESS_BASE[0x4].ADDR: 0 - 00000000 HLSQ_CS_BINDLESS_BASE[0x4].ADDR_HI: 0 - context: 1 00000001 HLSQ_FS_CNTL_0: { THREADSIZE = THREAD128 } 00000007 HLSQ_CONTROL_1_REG: 0x7 @@ -7353,17 +7124,11 @@ clusters: 00000001 HLSQ_CS_KERNEL_GROUP_Z: 0x1 40304000 HLSQ_LOAD_STATE_FRAG_CMD: 0x40304000 8c415430 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR: 0x8c415430 - 00000000 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR_HI: 0 00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR: 0 - 00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR_HI: 0 00000000 HLSQ_CS_BINDLESS_BASE[0x1].ADDR: 0 - 00000000 HLSQ_CS_BINDLESS_BASE[0x1].ADDR_HI: 0 00000000 HLSQ_CS_BINDLESS_BASE[0x2].ADDR: 0 - 00000000 HLSQ_CS_BINDLESS_BASE[0x2].ADDR_HI: 0 00000000 HLSQ_CS_BINDLESS_BASE[0x3].ADDR: 0 - 00000000 HLSQ_CS_BINDLESS_BASE[0x3].ADDR_HI: 0 00000000 HLSQ_CS_BINDLESS_BASE[0x4].ADDR: 0 - 00000000 HLSQ_CS_BINDLESS_BASE[0x4].ADDR_HI: 0 - cluster-name: CLUSTER_SP_PS - context: 0 deadbeef HLSQ_2D_EVENT_CMD: { STATE_ID = 0xbe | EVENT = 0x6f | 0xdead0080 } @@ -7374,11 +7139,9 @@ clusters: 05100000 SP_FS_CTRL_REG0: { THREADSIZE = THREAD128 | UNK24 | PIXLODENABLE | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 } 00000000 SP_FS_BRANCH_COND: 0 00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0 - 4bdb43d8 SP_FS_OBJ_START: 0x4bdb43d8 - 0001af86 SP_FS_OBJ_START_HI: 0x1af86 + 1af864bdb43d8 SP_FS_OBJ_START: 0x1af864bdb43d8 00000000 SP_FS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 } 00000000 SP_FS_PVT_MEM_ADDR: 0 - 00000000 SP_FS_PVT_MEM_ADDR_HI: 0 00000000 SP_FS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 } 00000100 SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 } 00000000 SP_SRGB_CNTL: { 0 } @@ -7417,10 +7180,8 @@ clusters: 00000000 SP_CS_BRANCH_COND: 0 00000000 SP_CS_OBJ_FIRST_EXEC_OFFSET: 0 8c415420 SP_CS_OBJ_START: 0x8c415420 - 00000000 SP_CS_OBJ_START_HI: 0 00000000 SP_CS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 } 00000000 SP_CS_PVT_MEM_ADDR: 0 - 00000000 SP_CS_PVT_MEM_ADDR+0x1: 0 00000000 SP_CS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 } 00000080 SP_CS_TEX_COUNT: 128 00200100 SP_CS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 16 | NIBO = 0 } @@ -7429,26 +7190,16 @@ clusters: 00000000 0xa9d1: 00000000 00000000 0xa9d2: 00000000 00000000 0xa9d3: 00000000 - efea5306 SP_FS_TEX_SAMP: 0xefea5306 - 00005e1c SP_FS_TEX_SAMP_HI: 0x5e1c - bf8b2a24 SP_CS_TEX_SAMP: 0xbf8b2a24 - 0001ef50 SP_CS_TEX_SAMP_HI: 0x1ef50 - 693f2108 SP_FS_TEX_CONST: 0x693f2108 - 00001998 SP_FS_TEX_CONST_HI: 0x1998 - be19e77a SP_CS_TEX_CONST: 0xbe19e77a - 0001b500 SP_CS_TEX_CONST_HI: 0x1b500 - 7dd2a41c SP_CS_BINDLESS_BASE[0].ADDR: 0x7dd2a41c - 00012191 SP_CS_BINDLESS_BASE[0].ADDR_HI: 0x12191 - 7d568030 SP_CS_BINDLESS_BASE[0x1].ADDR: 0x7d568030 - 0000f408 SP_CS_BINDLESS_BASE[0x1].ADDR_HI: 0xf408 - 6915b33d SP_CS_BINDLESS_BASE[0x2].ADDR: 0x6915b33d - 000076cd SP_CS_BINDLESS_BASE[0x2].ADDR_HI: 0x76cd - 3cfd0197 SP_CS_BINDLESS_BASE[0x3].ADDR: 0x3cfd0197 - 0001f233 SP_CS_BINDLESS_BASE[0x3].ADDR_HI: 0x1f233 - a6b745da SP_CS_BINDLESS_BASE[0x4].ADDR: 0xa6b745da - 00016204 SP_CS_BINDLESS_BASE[0x4].ADDR_HI: 0x16204 - fdfdd365 SP_CS_IBO: 0xfdfdd365 - 0001d693 SP_CS_IBO_HI: 0x1d693 + 5e1cefea5306 SP_FS_TEX_SAMP: 0x5e1cefea5306 + 1ef50bf8b2a24 SP_CS_TEX_SAMP: 0x1ef50bf8b2a24 + 1998693f2108 SP_FS_TEX_CONST: 0x1998693f2108 + 1b500be19e77a SP_CS_TEX_CONST: 0x1b500be19e77a + 121917dd2a41c SP_CS_BINDLESS_BASE[0].ADDR: 0x121917dd2a41c + f4087d568030 SP_CS_BINDLESS_BASE[0x1].ADDR: 0xf4087d568030 + 76cd6915b33d SP_CS_BINDLESS_BASE[0x2].ADDR: 0x76cd6915b33d + 1f2333cfd0197 SP_CS_BINDLESS_BASE[0x3].ADDR: 0x1f2333cfd0197 + 16204a6b745da SP_CS_BINDLESS_BASE[0x4].ADDR: 0x16204a6b745da + 1d693fdfdd365 SP_CS_IBO: 0x1d693fdfdd365 00000040 SP_CS_IBO_COUNT: 64 00000000 0xaa30: 00000000 00000000 0xaa31: 00000000 @@ -7456,11 +7207,9 @@ clusters: 05100000 SP_FS_CTRL_REG0: { THREADSIZE = THREAD128 | UNK24 | PIXLODENABLE | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 } 00000000 SP_FS_BRANCH_COND: 0 00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0 - 4bdb43d8 SP_FS_OBJ_START: 0x4bdb43d8 - 0001af86 SP_FS_OBJ_START_HI: 0x1af86 + 1af864bdb43d8 SP_FS_OBJ_START: 0x1af864bdb43d8 00000000 SP_FS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 } 00000000 SP_FS_PVT_MEM_ADDR: 0 - 00000000 SP_FS_PVT_MEM_ADDR_HI: 0 00000000 SP_FS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 } 00000100 SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 } 00000000 SP_SRGB_CNTL: { 0 } @@ -7499,10 +7248,8 @@ clusters: 00000000 SP_CS_BRANCH_COND: 0 00000000 SP_CS_OBJ_FIRST_EXEC_OFFSET: 0 8c415420 SP_CS_OBJ_START: 0x8c415420 - 00000000 SP_CS_OBJ_START_HI: 0 00000000 SP_CS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 } 00000000 SP_CS_PVT_MEM_ADDR: 0 - 00000000 SP_CS_PVT_MEM_ADDR+0x1: 0 00000000 SP_CS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 } 00000080 SP_CS_TEX_COUNT: 128 00200100 SP_CS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 16 | NIBO = 0 } @@ -7511,26 +7258,16 @@ clusters: 00000000 0xa9d1: 00000000 00000000 0xa9d2: 00000000 00000000 0xa9d3: 00000000 - efea5306 SP_FS_TEX_SAMP: 0xefea5306 - 00005e1c SP_FS_TEX_SAMP_HI: 0x5e1c - bf8b2a24 SP_CS_TEX_SAMP: 0xbf8b2a24 - 0001ef50 SP_CS_TEX_SAMP_HI: 0x1ef50 - 693f2108 SP_FS_TEX_CONST: 0x693f2108 - 00001998 SP_FS_TEX_CONST_HI: 0x1998 - be19e77a SP_CS_TEX_CONST: 0xbe19e77a - 0001b500 SP_CS_TEX_CONST_HI: 0x1b500 - 7dd2a41c SP_CS_BINDLESS_BASE[0].ADDR: 0x7dd2a41c - 00012191 SP_CS_BINDLESS_BASE[0].ADDR_HI: 0x12191 - 7d568030 SP_CS_BINDLESS_BASE[0x1].ADDR: 0x7d568030 - 0000f408 SP_CS_BINDLESS_BASE[0x1].ADDR_HI: 0xf408 - 6915b33d SP_CS_BINDLESS_BASE[0x2].ADDR: 0x6915b33d - 000076cd SP_CS_BINDLESS_BASE[0x2].ADDR_HI: 0x76cd - 3cfd0197 SP_CS_BINDLESS_BASE[0x3].ADDR: 0x3cfd0197 - 0001f233 SP_CS_BINDLESS_BASE[0x3].ADDR_HI: 0x1f233 - a6b745da SP_CS_BINDLESS_BASE[0x4].ADDR: 0xa6b745da - 00016204 SP_CS_BINDLESS_BASE[0x4].ADDR_HI: 0x16204 - fdfdd365 SP_CS_IBO: 0xfdfdd365 - 0001d693 SP_CS_IBO_HI: 0x1d693 + 5e1cefea5306 SP_FS_TEX_SAMP: 0x5e1cefea5306 + 1ef50bf8b2a24 SP_CS_TEX_SAMP: 0x1ef50bf8b2a24 + 1998693f2108 SP_FS_TEX_CONST: 0x1998693f2108 + 1b500be19e77a SP_CS_TEX_CONST: 0x1b500be19e77a + 121917dd2a41c SP_CS_BINDLESS_BASE[0].ADDR: 0x121917dd2a41c + f4087d568030 SP_CS_BINDLESS_BASE[0x1].ADDR: 0xf4087d568030 + 76cd6915b33d SP_CS_BINDLESS_BASE[0x2].ADDR: 0x76cd6915b33d + 1f2333cfd0197 SP_CS_BINDLESS_BASE[0x3].ADDR: 0x1f2333cfd0197 + 16204a6b745da SP_CS_BINDLESS_BASE[0x4].ADDR: 0x16204a6b745da + 1d693fdfdd365 SP_CS_IBO: 0x1d693fdfdd365 00000040 SP_CS_IBO_COUNT: 64 00000000 0xaa30: 00000000 00000000 0xaa31: 00000000 @@ -7542,14 +7279,12 @@ clusters: - cluster-name: CLUSTER_SP_PS - context: 0 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0 - 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR_HI: 0 00000000 SP_UNKNOWN_B182: 0 00000000 SP_UNKNOWN_B183: 0 00000000 SP_UNKNOWN_B190: 0 00000000 SP_UNKNOWN_B191: 0 - context: 1 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0 - 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR_HI: 0 00000000 SP_UNKNOWN_B182: 0 00000000 SP_UNKNOWN_B183: 0 00000000 SP_UNKNOWN_B190: 0 @@ -7559,15 +7294,11 @@ clusters: 00000000 SP_PS_2D_SRC_INFO: { COLOR_FORMAT = 0 | TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX | SAMPLES = MSAA_ONE } 00000000 SP_PS_2D_SRC_SIZE: { WIDTH = 0 | HEIGHT = 0 } 00000000 SP_PS_2D_SRC: 0 - 00000000 SP_PS_2D_SRC_HI: 0 00000000 SP_PS_2D_SRC_PITCH: { PITCH = 0 } 00000000 SP_PS_2D_SRC_PLANE1: 0 - 00000000 SP_PS_2D_SRC_PLANE1_HI: 0 00000000 SP_PS_2D_SRC_PLANE_PITCH: 0 00000000 SP_PS_2D_SRC_PLANE2: 0 - 00000000 SP_PS_2D_SRC_PLANE2_HI: 0 00000000 SP_PS_2D_SRC_FLAGS: 0 - 00000000 SP_PS_2D_SRC_FLAGS_HI: 0 00000000 SP_PS_2D_SRC_FLAGS_PITCH: 0 00000000 SP_PS_UNKNOWN_B4CD: 0 00000000 SP_PS_UNKNOWN_B4CE: 0 @@ -7578,15 +7309,11 @@ clusters: 00000000 SP_PS_2D_SRC_INFO: { COLOR_FORMAT = 0 | TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX | SAMPLES = MSAA_ONE } 00000000 SP_PS_2D_SRC_SIZE: { WIDTH = 0 | HEIGHT = 0 } 00000000 SP_PS_2D_SRC: 0 - 00000000 SP_PS_2D_SRC_HI: 0 00000000 SP_PS_2D_SRC_PITCH: { PITCH = 0 } 00000000 SP_PS_2D_SRC_PLANE1: 0 - 00000000 SP_PS_2D_SRC_PLANE1_HI: 0 00000000 SP_PS_2D_SRC_PLANE_PITCH: 0 00000000 SP_PS_2D_SRC_PLANE2: 0 - 00000000 SP_PS_2D_SRC_PLANE2_HI: 0 00000000 SP_PS_2D_SRC_FLAGS: 0 - 00000000 SP_PS_2D_SRC_FLAGS_HI: 0 00000000 SP_PS_2D_SRC_FLAGS_PITCH: 0 00000000 SP_PS_UNKNOWN_B4CD: 0 00000000 SP_PS_UNKNOWN_B4CE: 0 @@ -7598,69 +7325,46 @@ clusters: 00000140 HLSQ_FS_CNTL: { CONSTLEN = 256 | ENABLED } 00000000 HLSQ_SHARED_CONSTS: { 0 } 00000000 HLSQ_BINDLESS_BASE[0].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0].ADDR_HI: 0 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR_HI: 0 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR_HI: 0 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR_HI: 0 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR_HI: 0 - context: 1 00000140 HLSQ_FS_CNTL: { CONSTLEN = 256 | ENABLED } 00000000 HLSQ_SHARED_CONSTS: { 0 } 00000000 HLSQ_BINDLESS_BASE[0].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0].ADDR_HI: 0 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR_HI: 0 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR_HI: 0 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR_HI: 0 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR: 0 - 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR_HI: 0 - cluster-name: CLUSTER_SP_PS - context: 0 00000000 SP_MODE_CONTROL: { ISAMMODE = 0 } 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } 00000000 SP_FS_INSTRLEN: 0 - cdb94116 SP_BINDLESS_BASE[0].ADDR: 0xcdb94116 - 000007b4 SP_BINDLESS_BASE[0].ADDR_HI: 0x7b4 - 6e5e07c3 SP_BINDLESS_BASE[0x1].ADDR: 0x6e5e07c3 - 0001f54b SP_BINDLESS_BASE[0x1].ADDR_HI: 0x1f54b - 5f979543 SP_BINDLESS_BASE[0x2].ADDR: 0x5f979543 - 0001b455 SP_BINDLESS_BASE[0x2].ADDR_HI: 0x1b455 - a4d3a8cc SP_BINDLESS_BASE[0x3].ADDR: 0xa4d3a8cc - 00013f8c SP_BINDLESS_BASE[0x3].ADDR_HI: 0x13f8c - 1d337e76 SP_BINDLESS_BASE[0x4].ADDR: 0x1d337e76 - 0001ff60 SP_BINDLESS_BASE[0x4].ADDR_HI: 0x1ff60 - e0e8bc18 SP_IBO: 0xe0e8bc18 - 00010202 SP_IBO_HI: 0x10202 + 7b4cdb94116 SP_BINDLESS_BASE[0].ADDR: 0x7b4cdb94116 + 1f54b6e5e07c3 SP_BINDLESS_BASE[0x1].ADDR: 0x1f54b6e5e07c3 + 1b4555f979543 SP_BINDLESS_BASE[0x2].ADDR: 0x1b4555f979543 + 13f8ca4d3a8cc SP_BINDLESS_BASE[0x3].ADDR: 0x13f8ca4d3a8cc + 1ff601d337e76 SP_BINDLESS_BASE[0x4].ADDR: 0x1ff601d337e76 + 10202e0e8bc18 SP_IBO: 0x10202e0e8bc18 00000040 SP_IBO_COUNT: 64 - context: 1 00000000 SP_MODE_CONTROL: { ISAMMODE = 0 } 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } 00000000 SP_FS_INSTRLEN: 0 - cdb94116 SP_BINDLESS_BASE[0].ADDR: 0xcdb94116 - 000007b4 SP_BINDLESS_BASE[0].ADDR_HI: 0x7b4 - 6e5e07c3 SP_BINDLESS_BASE[0x1].ADDR: 0x6e5e07c3 - 0001f54b SP_BINDLESS_BASE[0x1].ADDR_HI: 0x1f54b - 5f979543 SP_BINDLESS_BASE[0x2].ADDR: 0x5f979543 - 0001b455 SP_BINDLESS_BASE[0x2].ADDR_HI: 0x1b455 - a4d3a8cc SP_BINDLESS_BASE[0x3].ADDR: 0xa4d3a8cc - 00013f8c SP_BINDLESS_BASE[0x3].ADDR_HI: 0x13f8c - 1d337e76 SP_BINDLESS_BASE[0x4].ADDR: 0x1d337e76 - 0001ff60 SP_BINDLESS_BASE[0x4].ADDR_HI: 0x1ff60 - e0e8bc18 SP_IBO: 0xe0e8bc18 - 00010202 SP_IBO_HI: 0x10202 + 7b4cdb94116 SP_BINDLESS_BASE[0].ADDR: 0x7b4cdb94116 + 1f54b6e5e07c3 SP_BINDLESS_BASE[0x1].ADDR: 0x1f54b6e5e07c3 + 1b4555f979543 SP_BINDLESS_BASE[0x2].ADDR: 0x1b4555f979543 + 13f8ca4d3a8cc SP_BINDLESS_BASE[0x3].ADDR: 0x13f8ca4d3a8cc + 1ff601d337e76 SP_BINDLESS_BASE[0x4].ADDR: 0x1ff601d337e76 + 10202e0e8bc18 SP_IBO: 0x10202e0e8bc18 00000040 SP_IBO_COUNT: 64 - cluster-name: CLUSTER_SP_PS - context: 0 00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000000 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000000 SP_TP_BORDER_COLOR_BASE_ADDR: 0 - 00000000 SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0 00000000 SP_TP_SAMPLE_CONFIG: { 0 } 00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } 00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } @@ -7673,7 +7377,6 @@ clusters: 00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000000 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE } 00000000 SP_TP_BORDER_COLOR_BASE_ADDR: 0 - 00000000 SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0 00000000 SP_TP_SAMPLE_CONFIG: { 0 } 00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } 00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } diff --git a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log index 33eef780071..d4f1a3f0f98 100644 --- a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log +++ b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log @@ -207,23 +207,18 @@ cmdstream[0]: 265 dwords 0000000001058214: 0000: 40889801 00000000 write SP_TP_BORDER_COLOR_BASE_ADDR (b302) SP_TP_BORDER_COLOR_BASE_ADDR: 0x1011000 - SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0 000000000105821c: 0000: 48b30202 01011000 00000000 write SP_PS_TP_BORDER_COLOR_BASE_ADDR (b180) SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0x1011000 - SP_PS_TP_BORDER_COLOR_BASE_ADDR_HI: 0 0000000001058228: 0000: 40b18002 01011000 00000000 write VSC_DRAW_STRM_SIZE_ADDRESS (0c03) VSC_DRAW_STRM_SIZE_ADDRESS: 0x10fd000 - VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0 0000000001058234: 0000: 480c0302 010fd000 00000000 write VSC_PRIM_STRM_ADDRESS (0c30) VSC_PRIM_STRM_ADDRESS: 0x105c000 - VSC_PRIM_STRM_ADDRESS_HI: 0 0000000001058240: 0000: 480c3002 0105c000 00000000 write VSC_DRAW_STRM_ADDRESS (0c34) VSC_DRAW_STRM_ADDRESS: 0x10dc800 - VSC_DRAW_STRM_ADDRESS_HI: 0 000000000105824c: 0000: 400c3402 010dc800 00000000 opcode: CP_EVENT_WRITE (46) (5 dwords) { EVENT = PC_CCU_FLUSH_COLOR_TS } @@ -263,12 +258,10 @@ cmdstream[0]: 265 dwords write RB_2D_DST_INFO (8c17) RB_2D_DST_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX | FLAGS | SAMPLES = MSAA_ONE } RB_2D_DST: 0x1013000 - RB_2D_DST_HI: 0 RB_2D_DST_PITCH: 1024 00000000010582b8: 0000: 408c1704 00001330 01013000 00000000 00000010 write RB_2D_DST_FLAGS (8c20) RB_2D_DST_FLAGS: 0x1012000 - RB_2D_DST_FLAGS_HI: 0 RB_2D_DST_FLAGS_PITCH: 64 | 0x4000 00000000010582cc: 0000: 488c2083 01012000 00000000 00004001 opcode: CP_BLIT (2c) (2 dwords) @@ -277,11 +270,8 @@ cmdstream[0]: 265 dwords skip_ib2: g=0, l=0 draw[0] register values !+ 010fd000 VSC_DRAW_STRM_SIZE_ADDRESS: 0x10fd000 - + 00000000 VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0 !+ 0105c000 VSC_PRIM_STRM_ADDRESS: 0x105c000 - + 00000000 VSC_PRIM_STRM_ADDRESS_HI: 0 !+ 010dc800 VSC_DRAW_STRM_ADDRESS: 0x10dc800 - + 00000000 VSC_DRAW_STRM_ADDRESS_HI: 0 !+ 03200000 UCHE_UNKNOWN_0E12: 0x3200000 !+ 00000004 UCHE_CLIENT_PF: { PERFSEL = 0x4 } + 00000000 GRAS_SU_CONSERVATIVE_RAS_CNTL: { SHIFTAMOUNT = 0 } @@ -311,10 +301,8 @@ cmdstream[0]: 265 dwords + 00000000 RB_2D_UNKNOWN_8C01: 0 !+ 00001330 RB_2D_DST_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX | FLAGS | SAMPLES = MSAA_ONE } !+ 01013000 RB_2D_DST: 0x1013000 - + 00000000 RB_2D_DST_HI: 0 !+ 00000010 RB_2D_DST_PITCH: 1024 !+ 01012000 RB_2D_DST_FLAGS: 0x1012000 - + 00000000 RB_2D_DST_FLAGS_HI: 0 !+ 00004001 RB_2D_DST_FLAGS_PITCH: 64 | 0x4000 + 00000000 RB_2D_SRC_SOLID_C0: 0 + 00000000 RB_2D_SRC_SOLID_C1: 0 @@ -352,11 +340,9 @@ cmdstream[0]: 265 dwords !+ 00000008 SP_FLOAT_CNTL: { F16_NO_INF } !+ 0000003f SP_PERFCTR_ENABLE: { VS | HS | DS | GS | FS | CS } !+ 01011000 SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0x1011000 - + 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR_HI: 0 + 00000000 SP_UNKNOWN_B182: 0 + 00000000 SP_UNKNOWN_B183: 0 !+ 01011000 SP_TP_BORDER_COLOR_BASE_ADDR: 0x1011000 - + 00000000 SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0 !+ 000000a2 SP_TP_MODE_CNTL: { ISAMMODE = ISAMMODE_GL | UNK3 = 0x28 } !+ 00100000 TPL1_DBG_ECO_CNTL: 0x100000 !+ 00000044 TPL1_UNKNOWN_B605: 68 @@ -465,12 +451,10 @@ cmdstream[0]: 265 dwords write RB_BLIT_DST_INFO (88d7) RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM } RB_BLIT_DST: 0x1013000 - RB_BLIT_DST_HI: 0 RB_BLIT_DST_PITCH: 1024 000000000115e028: 0000: 4888d704 00001807 01013000 00000000 00000010 write RB_BLIT_FLAG_DST (88dc) RB_BLIT_FLAG_DST: 0x1012000 - RB_BLIT_FLAG_DST_HI: 0 RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 } 000000000115e03c: 0000: 4088dc83 01012000 00000000 00004001 write RB_BLIT_BASE_GMEM (88d6) @@ -497,10 +481,8 @@ cmdstream[0]: 265 dwords + 00000000 RB_BLIT_BASE_GMEM: 0 !+ 00001807 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM } !+ 01013000 RB_BLIT_DST: 0x1013000 - + 00000000 RB_BLIT_DST_HI: 0 !+ 00000010 RB_BLIT_DST_PITCH: 1024 !+ 01012000 RB_BLIT_FLAG_DST: 0x1012000 - + 00000000 RB_BLIT_FLAG_DST_HI: 0 !+ 00004001 RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 } !+ 00000003 RB_BLIT_INFO: { UNK0 | GMEM | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 } !+ 7c400000 RB_CCU_CNTL: { COLOR_OFFSET = 0xf8000 | DEPTH_OFFSET = 0 | GMEM } @@ -521,7 +503,6 @@ cmdstream[0]: 265 dwords RB_DEPTH_BUFFER_PITCH: 0 RB_DEPTH_BUFFER_ARRAY_PITCH: 0 RB_DEPTH_BUFFER_BASE: 0 - RB_DEPTH_BUFFER_BASE_HI: 0 RB_DEPTH_BUFFER_BASE_GMEM: 0 000000000115e074: 0000: 48887286 00000000 00000000 00000000 00000000 00000000 00000000 write GRAS_SU_DEPTH_BUFFER_INFO (8098) @@ -529,10 +510,8 @@ cmdstream[0]: 265 dwords 000000000115e090: 0000: 48809801 00000000 write GRAS_LRZ_BUFFER_BASE (8103) GRAS_LRZ_BUFFER_BASE: 0 - GRAS_LRZ_BUFFER_BASE_HI: 0 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0 - GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0 000000000115e098: 0000: 48810385 00000000 00000000 00000000 00000000 00000000 write RB_STENCIL_INFO (8881) RB_STENCIL_INFO: { 0 } @@ -542,7 +521,6 @@ cmdstream[0]: 265 dwords RB_MRT[0].PITCH: 1024 RB_MRT[0].ARRAY_PITCH: 262144 RB_MRT[0].BASE: 0x1013000 - RB_MRT[0].BASE_HI: 0 RB_MRT[0].BASE_GMEM: 0 000000000115e0b8: 0000: 48882286 00000330 00000010 00001000 01013000 00000000 00000000 write SP_FS_MRT[0].REG (a996) @@ -550,7 +528,6 @@ cmdstream[0]: 265 dwords 000000000115e0d4: 0000: 48a99601 00000030 write RB_MRT_FLAG_BUFFER[0].ADDR (8903) RB_MRT_FLAG_BUFFER[0].ADDR: 0x1012000 - RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 } 000000000115e0dc: 0000: 40890383 01012000 00000000 00004001 write RB_SRGB_CNTL (880f) @@ -814,7 +791,6 @@ cmdstream[0]: 265 dwords - shaderdb: 0 last-baryf, 0 half, 3 full, 2 constlen - shaderdb: 8 cat0, 0 cat1, 1 cat2, 4 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 0 (sy) - SP_VS_OBJ_START_HI: 0 00000000010541a4: 0000: 48a81c02 01054000 00000000 opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords) { DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 } @@ -892,7 +868,6 @@ cmdstream[0]: 265 dwords - shaderdb: 3 last-baryf, 0 half, 2 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 0 (sy) - SP_FS_OBJ_START_HI: 0 000000000105422c: 0000: 40a98302 01054080 00000000 opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords) { DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_FS_SHADER | NUM_UNIT = 1 } @@ -1070,7 +1045,6 @@ cmdstream[0]: 265 dwords 000000000115c070: 0000: 40a01083 01053000 00000000 00000318 write VFD_FETCH[0].BASE (a010) VFD_FETCH[0].BASE: 0x1053000 - VFD_FETCH[0].BASE_HI: 0 VFD_FETCH[0].SIZE: 792 000000000115c070: 0000: 40a01083 01053000 00000000 00000318 group_id: 4 @@ -1341,10 +1315,8 @@ cmdstream[0]: 265 dwords !+ 00ff00ff GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 255 | Y = 255 } + 00000000 GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER } + 00000000 GRAS_LRZ_BUFFER_BASE: 0 - + 00000000 GRAS_LRZ_BUFFER_BASE_HI: 0 + 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0 - + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0 + 00000000 GRAS_SAMPLE_CNTL: { 0 } !+ 00010010 RB_RENDER_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | FLAG_MRTS = 0x1 } + 00000000 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE } @@ -1363,7 +1335,6 @@ cmdstream[0]: 265 dwords !+ 00000010 RB_MRT[0].PITCH: 1024 !+ 00001000 RB_MRT[0].ARRAY_PITCH: 262144 !+ 01013000 RB_MRT[0].BASE: 0x1013000 - + 00000000 RB_MRT[0].BASE_HI: 0 + 00000000 RB_MRT[0].BASE_GMEM: 0 !+ dffe8440 RB_BLEND_RED_F32: -36679707902607360000.000000 !+ 0000ffff RB_BLEND_GREEN_F32: 0.000000 @@ -1377,7 +1348,6 @@ cmdstream[0]: 265 dwords + 00000000 RB_DEPTH_BUFFER_PITCH: 0 + 00000000 RB_DEPTH_BUFFER_ARRAY_PITCH: 0 + 00000000 RB_DEPTH_BUFFER_BASE: 0 - + 00000000 RB_DEPTH_BUFFER_BASE_HI: 0 + 00000000 RB_DEPTH_BUFFER_BASE_GMEM: 0 + 00000000 RB_Z_BOUNDS_MIN: 0.000000 + 00000000 RB_Z_BOUNDS_MAX: 0.000000 @@ -1392,7 +1362,6 @@ cmdstream[0]: 265 dwords + 00ff00ff RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 } + 00000000 RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE } !+ 01012000 RB_MRT_FLAG_BUFFER[0].ADDR: 0x1012000 - + 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0 !+ 00004001 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 } !+ 00ffff00 VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 } !+ 0000ffff VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } @@ -1434,7 +1403,6 @@ cmdstream[0]: 265 dwords !+ 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | UNK8 = r63.x } + 00000000 VFD_CONTROL_6: { 0 } !+ 01053000 VFD_FETCH[0].BASE: 0x1053000 - + 00000000 VFD_FETCH[0].BASE_HI: 0 !+ 00000318 VFD_FETCH[0].SIZE: 792 !+ 00000024 VFD_FETCH[0].STRIDE: 36 !+ c8200000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT } @@ -1472,7 +1440,6 @@ cmdstream[0]: 265 dwords - shaderdb: 0 last-baryf, 0 half, 3 full, 2 constlen - shaderdb: 8 cat0, 0 cat1, 1 cat2, 4 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 0 (sy) - + 00000000 SP_VS_OBJ_START_HI: 0 !+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } !+ 00000001 SP_VS_INSTRLEN: 1 + 00000000 SP_HS_WAVE_INPUT_SIZE: 0 @@ -1500,7 +1467,6 @@ cmdstream[0]: 265 dwords - shaderdb: 3 last-baryf, 0 half, 2 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 0 (sy) - + 00000000 SP_FS_OBJ_START_HI: 0 !+ 00000100 SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 } + 00000000 SP_SRGB_CNTL: { 0 } !+ 0000000f SP_FS_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 } @@ -1564,12 +1530,10 @@ cmdstream[0]: 265 dwords write RB_BLIT_DST_INFO (88d7) RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM } RB_BLIT_DST: 0x1013000 - RB_BLIT_DST_HI: 0 RB_BLIT_DST_PITCH: 1024 000000000115c03c: 0000: 4888d704 00001807 01013000 00000000 00000010 write RB_BLIT_FLAG_DST (88dc) RB_BLIT_FLAG_DST: 0x1012000 - RB_BLIT_FLAG_DST_HI: 0 RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 } 000000000115c050: 0000: 4088dc83 01012000 00000000 00004001 write RB_BLIT_BASE_GMEM (88d6) @@ -1587,10 +1551,8 @@ cmdstream[0]: 265 dwords + 00000000 RB_BLIT_BASE_GMEM: 0 + 00001807 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM } + 01013000 RB_BLIT_DST: 0x1013000 - + 00000000 RB_BLIT_DST_HI: 0 + 00000010 RB_BLIT_DST_PITCH: 1024 + 01012000 RB_BLIT_FLAG_DST: 0x1012000 - + 00000000 RB_BLIT_FLAG_DST_HI: 0 + 00004001 RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 } !+ 00000000 RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 } 000000000115c068: 0000: 70460001 0000001e diff --git a/src/freedreno/.gitlab-ci/reference/fd-clouds.log b/src/freedreno/.gitlab-ci/reference/fd-clouds.log index 3f18ad0289b..b95c0388955 100644 --- a/src/freedreno/.gitlab-ci/reference/fd-clouds.log +++ b/src/freedreno/.gitlab-ci/reference/fd-clouds.log @@ -252,7 +252,6 @@ cmdstream[0]: 1023 dwords RB_DEPTH_BUFFER_PITCH: 0 RB_DEPTH_BUFFER_ARRAY_PITCH: 0 RB_DEPTH_BUFFER_BASE: 0 - RB_DEPTH_BUFFER_BASE_HI: 0 RB_DEPTH_BUFFER_BASE_GMEM: 0 0000000001d91284: 0000: 48887286 00000000 00000000 00000000 00000000 00000000 00000000 write GRAS_SU_DEPTH_BUFFER_INFO (8098) @@ -260,10 +259,8 @@ cmdstream[0]: 1023 dwords 0000000001d912a0: 0000: 48809801 00000000 write GRAS_LRZ_BUFFER_BASE (8103) GRAS_LRZ_BUFFER_BASE: 0 - GRAS_LRZ_BUFFER_BASE_HI: 0 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0 - GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0 0000000001d912a8: 0000: 48810385 00000000 00000000 00000000 00000000 00000000 write RB_STENCIL_INFO (8881) RB_STENCIL_INFO: { 0 } @@ -273,7 +270,6 @@ cmdstream[0]: 1023 dwords RB_MRT[0].PITCH: 8704 RB_MRT[0].ARRAY_PITCH: 12533760 RB_MRT[0].BASE: 0x1125000 - RB_MRT[0].BASE_HI: 0 RB_MRT[0].BASE_GMEM: 0 0000000001d912c8: 0000: 48882286 00002031 00000088 0002fd00 01125000 00000000 00000000 write SP_FS_MRT[0].REG (a996) @@ -281,7 +277,6 @@ cmdstream[0]: 1023 dwords 0000000001d912e4: 0000: 48a99601 00000031 write RB_MRT_FLAG_BUFFER[0].ADDR (8903) RB_MRT_FLAG_BUFFER[0].ADDR: 0 - RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 0000000001d912ec: 0000: 40890383 00000000 00000000 00000000 write RB_SRGB_CNTL (880f) @@ -365,7 +360,6 @@ cmdstream[0]: 1023 dwords write VSC_BIN_SIZE (0c02) VSC_BIN_SIZE: { WIDTH = 544 | HEIGHT = 480 } VSC_DRAW_STRM_SIZE_ADDRESS: 0x1d65800 - VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0 0000000001d913d4: 0000: 400c0283 00001e11 01d65800 00000000 write VSC_BIN_COUNT (0c06) VSC_BIN_COUNT: { NX = 4 | NY = 3 } @@ -408,13 +402,11 @@ cmdstream[0]: 1023 dwords * write VSC_PRIM_STRM_ADDRESS (0c30) VSC_PRIM_STRM_ADDRESS: 0x1d67000 - VSC_PRIM_STRM_ADDRESS_HI: 0 VSC_PRIM_STRM_PITCH: 0x1040 VSC_PRIM_STRM_LIMIT: 0x28000 0000000001d91470: 0000: 480c3004 01d67000 00000000 00001040 00028000 write VSC_DRAW_STRM_ADDRESS (0c34) VSC_DRAW_STRM_ADDRESS: 0x1d5d000 - VSC_DRAW_STRM_ADDRESS_HI: 0 VSC_DRAW_STRM_PITCH: 0x440 VSC_DRAW_STRM_LIMIT: 0xa000 0000000001d91484: 0000: 400c3404 01d5d000 00000000 00000440 0000a000 @@ -637,7 +629,6 @@ cmdstream[0]: 1023 dwords - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 0 (sy) - SP_VS_OBJ_START_HI: 0 0000000001121038: 0000: 48a81c02 01011000 00000000 opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords) { DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 } @@ -779,7 +770,6 @@ cmdstream[0]: 1023 dwords 0000000001116020: 0020: 40a0d001 0000000f 48a00001 00000101 write VFD_FETCH[0].BASE (a010) VFD_FETCH[0].BASE: 0x1016000 - VFD_FETCH[0].BASE_HI: 0 VFD_FETCH[0].SIZE: 1048576 VFD_FETCH[0].STRIDE: 12 0000000001116000: 0000: 40a01004 01016000 00000000 00100000 0000000c @@ -875,7 +865,6 @@ cmdstream[0]: 1023 dwords :0,1,11,2 !+ 00001e11 VSC_BIN_SIZE: { WIDTH = 544 | HEIGHT = 480 } !+ 01d65800 VSC_DRAW_STRM_SIZE_ADDRESS: 0x1d65800 - + 00000000 VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0 !+ 00001808 VSC_BIN_COUNT: { NX = 4 | NY = 3 } !+ 04100000 VSC_PIPE_CONFIG[0].REG: { X = 0 | Y = 0 | W = 1 | H = 1 } !+ 04100001 VSC_PIPE_CONFIG[0x1].REG: { X = 1 | Y = 0 | W = 1 | H = 1 } @@ -910,11 +899,9 @@ cmdstream[0]: 1023 dwords + 00000000 VSC_PIPE_CONFIG[0x1e].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } + 00000000 VSC_PIPE_CONFIG[0x1f].REG: { X = 0 | Y = 0 | W = 0 | H = 0 } !+ 01d67000 VSC_PRIM_STRM_ADDRESS: 0x1d67000 - + 00000000 VSC_PRIM_STRM_ADDRESS_HI: 0 !+ 00001040 VSC_PRIM_STRM_PITCH: 0x1040 !+ 00028000 VSC_PRIM_STRM_LIMIT: 0x28000 !+ 01d5d000 VSC_DRAW_STRM_ADDRESS: 0x1d5d000 - + 00000000 VSC_DRAW_STRM_ADDRESS_HI: 0 !+ 00000440 VSC_DRAW_STRM_PITCH: 0x440 !+ 0000a000 VSC_DRAW_STRM_LIMIT: 0xa000 !+ 03200000 UCHE_UNKNOWN_0E12: 0x3200000 @@ -957,10 +944,8 @@ cmdstream[0]: 1023 dwords + 00000000 GRAS_LRZ_CNTL: { DIR = 0 } + 00000000 GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER } + 00000000 GRAS_LRZ_BUFFER_BASE: 0 - + 00000000 GRAS_LRZ_BUFFER_BASE_HI: 0 + 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0 - + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0 + 00000000 GRAS_SAMPLE_CNTL: { 0 } !+ 00000002 GRAS_UNKNOWN_8110: 0x2 + 00000000 GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 } @@ -990,7 +975,6 @@ cmdstream[0]: 1023 dwords !+ 00000088 RB_MRT[0].PITCH: 8704 !+ 0002fd00 RB_MRT[0].ARRAY_PITCH: 12533760 !+ 01125000 RB_MRT[0].BASE: 0x1125000 - + 00000000 RB_MRT[0].BASE_HI: 0 + 00000000 RB_MRT[0].BASE_GMEM: 0 + 00000000 RB_BLEND_RED_F32: 0.000000 + 00000000 RB_BLEND_GREEN_F32: 0.000000 @@ -1004,7 +988,6 @@ cmdstream[0]: 1023 dwords + 00000000 RB_DEPTH_BUFFER_PITCH: 0 + 00000000 RB_DEPTH_BUFFER_ARRAY_PITCH: 0 + 00000000 RB_DEPTH_BUFFER_BASE: 0 - + 00000000 RB_DEPTH_BUFFER_BASE_HI: 0 + 00000000 RB_DEPTH_BUFFER_BASE_GMEM: 0 + 00000000 RB_Z_BOUNDS_MIN: 0.000000 + 00000000 RB_Z_BOUNDS_MAX: 0.000000 @@ -1019,7 +1002,6 @@ cmdstream[0]: 1023 dwords + 00000000 RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE } + 00000000 RB_UNKNOWN_88F0: 0 + 00000000 RB_MRT_FLAG_BUFFER[0].ADDR: 0 - + 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0 + 00000000 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } !+ 00000001 RB_UNKNOWN_8E01: 0x1 + 00000000 RB_DBG_ECO_CNTL: 0 @@ -1068,7 +1050,6 @@ cmdstream[0]: 1023 dwords + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 VFD_INSTANCE_START_OFFSET: 0 !+ 01016000 VFD_FETCH[0].BASE: 0x1016000 - + 00000000 VFD_FETCH[0].BASE_HI: 0 !+ 00100000 VFD_FETCH[0].SIZE: 1048576 !+ 0000000c VFD_FETCH[0].STRIDE: 12 !+ c7400000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT } @@ -1093,7 +1074,6 @@ cmdstream[0]: 1023 dwords - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 0 (sy) - + 00000000 SP_VS_OBJ_START_HI: 0 !+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } !+ 00000001 SP_VS_INSTRLEN: 1 + 00000000 SP_HS_WAVE_INPUT_SIZE: 0 @@ -1931,7 +1911,6 @@ cmdstream[0]: 1023 dwords - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 0 (sy) - SP_VS_OBJ_START_HI: 0 0000000001120038: 0000: 48a81c02 01012000 00000000 opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords) { DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 } @@ -3464,7 +3443,6 @@ cmdstream[0]: 1023 dwords - shaderdb: 0 last-baryf, 0 half, 19 full, 29 constlen - shaderdb: 1120 cat0, 48 cat1, 551 cat2, 512 cat3, 183 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 1326 sstall, 140 (ss), 0 (sy) - SP_FS_OBJ_START_HI: 0 0000000001120158: 0000: 40a98302 01013000 00000000 opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords) { DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_FS_SHADER | NUM_UNIT = 88 } @@ -4996,7 +4974,6 @@ cmdstream[0]: 1023 dwords 0000000001116020: 0020: 40a0d001 0000000f 48a00001 00000101 write VFD_FETCH[0].BASE (a010) VFD_FETCH[0].BASE: 0x1016000 - VFD_FETCH[0].BASE_HI: 0 VFD_FETCH[0].SIZE: 1048576 VFD_FETCH[0].STRIDE: 12 0000000001116000: 0000: 40a01004 01016000 00000000 00100000 0000000c @@ -5043,7 +5020,6 @@ cmdstream[0]: 1023 dwords 00000000011160a0: 0000: 70b68003 003a0000 011160a0 00000000 write SP_IBO (ab1a) SP_IBO: 0x11160a0 base=1116000, offset=160, size=388 - SP_IBO_HI: 0 00000000011160b0: 0000: 48ab1a02 011160a0 00000000 write SP_IBO_COUNT (ab20) SP_IBO_COUNT: 0 @@ -5268,7 +5244,6 @@ cmdstream[0]: 1023 dwords + 00000000 VFD_INDEX_OFFSET: 0 + 00000000 VFD_INSTANCE_START_OFFSET: 0 + 01016000 VFD_FETCH[0].BASE: 0x1016000 - + 00000000 VFD_FETCH[0].BASE_HI: 0 + 00100000 VFD_FETCH[0].SIZE: 1048576 + 0000000c VFD_FETCH[0].STRIDE: 12 + c7400000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT } @@ -5291,7 +5266,6 @@ cmdstream[0]: 1023 dwords - shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen - shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 0 sstall, 0 (ss), 0 (sy) - + 00000000 SP_VS_OBJ_START_HI: 0 + 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } + 00000001 SP_VS_INSTRLEN: 1 + 00000000 SP_HS_WAVE_INPUT_SIZE: 0 @@ -6726,7 +6700,6 @@ cmdstream[0]: 1023 dwords - shaderdb: 0 last-baryf, 0 half, 19 full, 29 constlen - shaderdb: 1120 cat0, 48 cat1, 551 cat2, 512 cat3, 183 cat4, 0 cat5, 0 cat6, 0 cat7 - shaderdb: 1326 sstall, 140 (ss), 0 (sy) - + 00000000 SP_FS_OBJ_START_HI: 0 !+ 00000100 SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 } + fcfcfc00 SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x } !+ 00000001 SP_FS_OUTPUT_CNTL1: { MRT = 1 } @@ -6744,7 +6717,6 @@ cmdstream[0]: 1023 dwords + 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 } !+ 00000058 SP_FS_INSTRLEN: 88 !+ 011160a0 SP_IBO: 0x11160a0 base=1116000, offset=160, size=388 - + 00000000 SP_IBO_HI: 0 + 00000000 SP_IBO_COUNT: 0 + 00000100 HLSQ_VS_CNTL: { CONSTLEN = 0 | ENABLED } + 00000000 HLSQ_HS_CNTL: { CONSTLEN = 0 } @@ -6823,7 +6795,6 @@ cmdstream[0]: 1023 dwords write RB_BLIT_DST_INFO (88d7) RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WXYZ | COLOR_FORMAT = FMT6_8_8_8_X8_UNORM } RB_BLIT_DST: 0x1125000 - RB_BLIT_DST_HI: 0 RB_BLIT_DST_PITCH: 8704 RB_BLIT_DST_ARRAY_PITCH: 12533760 0000000001116144: 0000: 4888d785 000018a0 01125000 00000000 00000088 0002fd00 @@ -6851,7 +6822,6 @@ cmdstream[0]: 1023 dwords + 00000000 RB_BLIT_BASE_GMEM: 0 !+ 000018a0 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WXYZ | COLOR_FORMAT = FMT6_8_8_8_X8_UNORM } !+ 01125000 RB_BLIT_DST: 0x1125000 - + 00000000 RB_BLIT_DST_HI: 0 !+ 00000088 RB_BLIT_DST_PITCH: 8704 !+ 0002fd00 RB_BLIT_DST_ARRAY_PITCH: 12533760 !+ 00000000 RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 } diff --git a/src/freedreno/decode/cffdec.c b/src/freedreno/decode/cffdec.c index a5706f16999..d967397bdea 100644 --- a/src/freedreno/decode/cffdec.c +++ b/src/freedreno/decode/cffdec.c @@ -815,14 +815,60 @@ endswith(uint32_t regbase, const char *suffix) return (s - strlen(name) + strlen(suffix)) == name; } -void -dump_register_val(uint32_t regbase, uint32_t dword, int level) +struct regacc +regacc(struct rnn *r) { - struct rnndecaddrinfo *info = rnn_reginfo(rnn, regbase); + if (!r) + r = rnn; + + return (struct regacc){ .rnn = r }; +} + +/* returns true if the complete reg value has been accumulated: */ +bool +regacc_push(struct regacc *r, uint32_t regbase, uint32_t dword) +{ + if (r->has_dword_lo) { + /* Work around kernel devcore dumps which accidentially miss half of a 64b reg + * see: https://patchwork.freedesktop.org/series/112302/ + */ + if (regbase != r->regbase + 1) { + printf("WARNING: 64b discontinuity (%x, expected %x)\n", regbase, r->regbase + 1); + r->has_dword_lo = false; + return true; + } + + r->value |= ((uint64_t)dword) << 32; + r->has_dword_lo = false; + + return true; + } + + r->regbase = regbase; + r->value = dword; + + struct rnndecaddrinfo *info = rnn_reginfo(r->rnn, regbase); + r->has_dword_lo = (info->width == 64); + + /* Workaround for kernel devcore dump bugs: */ + if ((info->width == 64) && endswith(regbase, "_HI")) { + printf("WARNING: 64b discontinuity (no _LO dword for %x)\n", regbase); + r->has_dword_lo = false; + } + + rnn_reginfo_free(info); + + return !r->has_dword_lo; +} + +void +dump_register_val(struct regacc *r, int level) +{ + struct rnndecaddrinfo *info = rnn_reginfo(rnn, r->regbase); if (info && info->typeinfo) { uint64_t gpuaddr = 0; - char *decoded = rnndec_decodeval(rnn->vc, info->typeinfo, dword); + char *decoded = rnndec_decodeval(rnn->vc, info->typeinfo, r->value); printf("%s%s: %s", levels[level], info->name, decoded); /* Try and figure out if we are looking at a gpuaddr.. this @@ -834,13 +880,18 @@ dump_register_val(uint32_t regbase, uint32_t dword, int level) if (options->gpu_id >= 600) { if (!strcmp(info->typeinfo->name, "address") || !strcmp(info->typeinfo->name, "waddress")) { - gpuaddr = (((uint64_t)reg_val(regbase + 1)) << 32) | dword; + gpuaddr = r->value; } } else if (options->gpu_id >= 500) { - if (endswith(regbase, "_HI") && endswith(regbase - 1, "_LO")) { - gpuaddr = (((uint64_t)dword) << 32) | reg_val(regbase - 1); - } else if (endswith(regbase, "_LO") && endswith(regbase + 1, "_HI")) { - gpuaddr = (((uint64_t)reg_val(regbase + 1)) << 32) | dword; + /* TODO we shouldn't rely on reg_val() since reg_set() might + * not have been called yet for the other half of the 64b reg. + * We can remove this hack once a5xx.xml is converted to reg64 + * and address/waddess. + */ + if (endswith(r->regbase, "_HI") && endswith(r->regbase - 1, "_LO")) { + gpuaddr = (r->value << 32) | reg_val(r->regbase - 1); + } else if (endswith(r->regbase, "_LO") && endswith(r->regbase + 1, "_HI")) { + gpuaddr = (((uint64_t)reg_val(r->regbase + 1)) << 32) | r->value; } } @@ -854,28 +905,27 @@ dump_register_val(uint32_t regbase, uint32_t dword, int level) free(decoded); } else if (info) { - printf("%s%s: %08x\n", levels[level], info->name, dword); + printf("%s%s: %08"PRIx64"\n", levels[level], info->name, r->value); } else { - printf("%s<%04x>: %08x\n", levels[level], regbase, dword); + printf("%s<%04x>: %08"PRIx64"\n", levels[level], r->regbase, r->value); } rnn_reginfo_free(info); } static void -dump_register(uint32_t regbase, uint32_t dword, int level) +dump_register(struct regacc *r, int level) { if (!quiet(3)) { - dump_register_val(regbase, dword, level); + dump_register_val(r, level); } for (unsigned idx = 0; type0_reg[idx].regname; idx++) { - if (type0_reg[idx].regbase == regbase) { + if (type0_reg[idx].regbase == r->regbase) { if (type0_reg[idx].is_reg64) { - uint64_t qword = (((uint64_t)reg_val(regbase + 1)) << 32) | dword; - type0_reg[idx].fxn64(type0_reg[idx].regname, qword, level); + type0_reg[idx].fxn64(type0_reg[idx].regname, r->value, level); } else { - type0_reg[idx].fxn(type0_reg[idx].regname, dword, level); + type0_reg[idx].fxn(type0_reg[idx].regname, (uint32_t)r->value, level); } break; } @@ -892,6 +942,8 @@ static void dump_registers(uint32_t regbase, uint32_t *dwords, uint32_t sizedwords, int level) { + struct regacc r = regacc(NULL); + while (sizedwords--) { int last_summary = summary; @@ -902,7 +954,8 @@ dump_registers(uint32_t regbase, uint32_t *dwords, uint32_t sizedwords, printl(2, "NEEDS WFI: %s (%x)\n", regname(regbase, 1), regbase); reg_set(regbase, *dwords); - dump_register(regbase, *dwords, level); + if (regacc_push(&r, regbase, *dwords)) + dump_register(&r, level); regbase++; dwords++; summary = last_summary; @@ -1030,26 +1083,33 @@ __do_query(const char *primtype, uint32_t num_indices) for (int i = 0; i < options->nquery; i++) { uint32_t regbase = queryvals[i]; - if (reg_written(regbase)) { - uint32_t lastval = reg_val(regbase); - printf("%4d: %s(%u,%u-%u,%u):%u:", draw_count, primtype, bin_x1, - bin_y1, bin_x2, bin_y2, num_indices); - if (options->gpu_id >= 500) - printf("%s:", render_mode); - printf("\t%08x", lastval); - if (lastval != lastvals[regbase]) { - printf("!"); - } else { - printf(" "); - } - if (reg_rewritten(regbase)) { - printf("+"); - } else { - printf(" "); - } - dump_register_val(regbase, lastval, 0); - n++; + if (!reg_written(regbase)) + continue; + + struct regacc r = regacc(NULL); + + /* 64b regs require two successive 32b dwords: */ + for (int d = 0; d < 2; d++) + if (regacc_push(&r, regbase + d, reg_val(regbase + d))) + break; + + printf("%4d: %s(%u,%u-%u,%u):%u:", draw_count, primtype, bin_x1, + bin_y1, bin_x2, bin_y2, num_indices); + if (options->gpu_id >= 500) + printf("%s:", render_mode); + printf("\t%08"PRIx64, r.value); + if (r.value != lastvals[regbase]) { + printf("!"); + } else { + printf(" "); } + if (reg_rewritten(regbase)) { + printf("+"); + } else { + printf(" "); + } + dump_register_val(&r, 0); + n++; } if (n > 1) @@ -1157,9 +1217,10 @@ static void cp_wide_reg_write(uint32_t *dwords, uint32_t sizedwords, int level) { uint32_t reg = dwords[0] & 0xffff; - int i; - for (i = 1; i < sizedwords; i++) { - dump_register(reg, dwords[i], level + 1); + struct regacc r = regacc(NULL); + for (int i = 1; i < sizedwords; i++) { + if (regacc_push(&r, reg, dwords[i])) + dump_register(&r, level + 1); reg_set(reg, dwords[i]); reg++; } @@ -1831,8 +1892,14 @@ dump_register_summary(int level) in_summary = true; + struct regacc r = regacc(NULL); + /* dump current state of registers: */ printl(2, "%sdraw[%i] register values\n", levels[level], draw_count); + + bool changed = false; + bool written = false; + for (i = 0; i < regcnt(); i++) { uint32_t regbase = i; uint32_t lastval = reg_val(regbase); @@ -1842,19 +1909,29 @@ dump_register_summary(int level) if (!reg_written(regbase)) continue; if (lastval != lastvals[regbase]) { - printl(2, "!"); + changed |= true; lastvals[regbase] = lastval; - } else { - printl(2, " "); } if (reg_rewritten(regbase)) { - printl(2, "+"); - } else { - printl(2, " "); + written |= true; } - printl(2, "\t%08x", lastval); if (!quiet(2)) { - dump_register(regbase, lastval, level); + if (regacc_push(&r, regbase, lastval)) { + if (changed) { + printl(2, "!"); + } else { + printl(2, " "); + } + if (written) { + printl(2, "+"); + } else { + printl(2, " "); + } + printl(2, "\t%08"PRIx64, r.value); + dump_register(&r, level); + + changed = written = false; + } } } @@ -2616,8 +2693,11 @@ cp_context_reg_bunch(uint32_t *dwords, uint32_t sizedwords, int level) bool saved_summary = summary; summary = false; + struct regacc r = regacc(NULL); + for (i = 0; i < sizedwords; i += 2) { - dump_register(dwords[i + 0], dwords[i + 1], level + 1); + if (regacc_push(&r, dwords[i + 0], dwords[i + 1])) + dump_register(&r, level + 1); reg_set(dwords[i + 0], dwords[i + 1]); } @@ -2629,7 +2709,9 @@ cp_reg_write(uint32_t *dwords, uint32_t sizedwords, int level) { uint32_t reg = dwords[1] & 0xffff; - dump_register(reg, dwords[2], level + 1); + struct regacc r = regacc(NULL); + if (regacc_push(&r, reg, dwords[2])) + dump_register(&r, level + 1); reg_set(reg, dwords[2]); } diff --git a/src/freedreno/decode/cffdec.h b/src/freedreno/decode/cffdec.h index 377a67797f8..3c96562aedb 100644 --- a/src/freedreno/decode/cffdec.h +++ b/src/freedreno/decode/cffdec.h @@ -81,6 +81,33 @@ struct cffdec_options { } ibs[4]; }; +/** + * A helper to deal with 64b registers by accumulating the lo/hi 32b + * dwords. Example usage: + * + * struct regacc r = regacc(rnn); + * + * for (dword in dwords) { + * if (regacc_push(&r, regbase, dword)) { + * printf("\t%08x"PRIx64", r.value); + * dump_register_val(r.regbase, r.value, 0); + * } + * regbase++; + * } + * + * It is expected that 64b regs will come in pairs of . + */ +struct regacc { + uint32_t regbase; + uint64_t value; + + /* private: */ + struct rnn *rnn; + bool has_dword_lo; +}; +struct regacc regacc(struct rnn *rnn); +bool regacc_push(struct regacc *regacc, uint32_t regbase, uint32_t dword); + void printl(int lvl, const char *fmt, ...); const char *pktname(unsigned opc); uint32_t regbase(const char *name); @@ -91,7 +118,7 @@ uint32_t reg_val(uint32_t regbase); void reg_set(uint32_t regbase, uint32_t val); void reset_regs(void); void cffdec_init(const struct cffdec_options *options); -void dump_register_val(uint32_t regbase, uint32_t dword, int level); +void dump_register_val(struct regacc *r, int level); void dump_commands(uint32_t *dwords, uint32_t sizedwords, int level); /* diff --git a/src/freedreno/decode/crashdec-mempool.c b/src/freedreno/decode/crashdec-mempool.c index 51f9159c1af..cee95c76edb 100644 --- a/src/freedreno/decode/crashdec-mempool.c +++ b/src/freedreno/decode/crashdec-mempool.c @@ -29,6 +29,12 @@ static void dump_mem_pool_reg_write(unsigned reg, uint32_t data, unsigned context, bool pipe) { + /* TODO deal better somehow w/ 64b regs: */ + struct regacc r = { + .rnn = pipe ? rnn_pipe : NULL, + .regbase = reg, + .value = data, + }; if (pipe) { struct rnndecaddrinfo *info = rnn_reginfo(rnn_pipe, reg); printf("\t\twrite %s (%02x) pipe\n", info->name, reg); @@ -37,12 +43,12 @@ dump_mem_pool_reg_write(unsigned reg, uint32_t data, unsigned context, /* registers that ignore their payload */ } else { printf("\t\t\t"); - dump_register(rnn_pipe, reg, data); + dump_register(&r); } rnn_reginfo_free(info); } else { printf("\t\twrite %s (%05x) context %d\n", regname(reg, 1), reg, context); - dump_register_val(reg, data, 2); + dump_register_val(&r, 2); } } diff --git a/src/freedreno/decode/crashdec.c b/src/freedreno/decode/crashdec.c index 640f8d49d2c..3110dc8e1a2 100644 --- a/src/freedreno/decode/crashdec.c +++ b/src/freedreno/decode/crashdec.c @@ -458,16 +458,16 @@ decode_bos(void) */ void -dump_register(struct rnn *rnn, uint32_t offset, uint32_t value) +dump_register(struct regacc *r) { - struct rnndecaddrinfo *info = rnn_reginfo(rnn, offset); + struct rnndecaddrinfo *info = rnn_reginfo(r->rnn, r->regbase); if (info && info->typeinfo) { - char *decoded = rnndec_decodeval(rnn->vc, info->typeinfo, value); + char *decoded = rnndec_decodeval(r->rnn->vc, info->typeinfo, r->value); printf("%s: %s\n", info->name, decoded); } else if (info) { - printf("%s: %08x\n", info->name, value); + printf("%s: %08"PRIx64"\n", info->name, r->value); } else { - printf("<%04x>: %08x\n", offset, value); + printf("<%04x>: %08"PRIx64"\n", r->regbase, r->value); } rnn_reginfo_free(info); } @@ -475,25 +475,33 @@ dump_register(struct rnn *rnn, uint32_t offset, uint32_t value) static void decode_gmu_registers(void) { + struct regacc r = regacc(rnn_gmu); + foreach_line_in_section (line) { uint32_t offset, value; parseline(line, " - { offset: %x, value: %x }", &offset, &value); - printf("\t%08x\t", value); - dump_register(rnn_gmu, offset / 4, value); + if (regacc_push(&r, offset / 4, value)) { + printf("\t%08"PRIx64"\t", r.value); + dump_register(&r); + } } } static void decode_registers(void) { + struct regacc r = regacc(NULL); + foreach_line_in_section (line) { uint32_t offset, value; parseline(line, " - { offset: %x, value: %x }", &offset, &value); reg_set(offset / 4, value); - printf("\t%08x", value); - dump_register_val(offset / 4, value, 0); + if (regacc_push(&r, offset / 4, value)) { + printf("\t%08"PRIx64, r.value); + dump_register_val(&r, 0); + } } } @@ -501,6 +509,8 @@ decode_registers(void) static void decode_clusters(void) { + struct regacc r = regacc(NULL); + foreach_line_in_section (line) { if (startswith(line, " - cluster-name:") || startswith(line, " - context:")) { @@ -511,8 +521,10 @@ decode_clusters(void) uint32_t offset, value; parseline(line, " - { offset: %x, value: %x }", &offset, &value); - printf("\t%08x", value); - dump_register_val(offset / 4, value, 0); + if (regacc_push(&r, offset / 4, value)) { + printf("\t%08"PRIx64, r.value); + dump_register_val(&r, 0); + } } } @@ -550,14 +562,18 @@ dump_control_regs(uint32_t *regs) if (!rnn_control) return; + struct regacc r = regacc(rnn_control); + /* Control regs 0x100-0x17f are a scratch space to be used by the * firmware however it wants, unlike lower regs which involve some * fixed-function units. Therefore only these registers get dumped * directly. */ for (uint32_t i = 0; i < 0x80; i++) { - printf("\t%08x\t", regs[i]); - dump_register(rnn_control, i + 0x100, regs[i]); + if (regacc_push(&r, i + 0x100, regs[i])) { + printf("\t%08"PRIx64"\t", r.value); + dump_register(&r); + } } } diff --git a/src/freedreno/decode/crashdec.h b/src/freedreno/decode/crashdec.h index c92afacce12..3060b10be2e 100644 --- a/src/freedreno/decode/crashdec.h +++ b/src/freedreno/decode/crashdec.h @@ -84,7 +84,7 @@ is_gmu_legacy(void) } } -void dump_register(struct rnn *rnn, uint32_t offset, uint32_t value); +void dump_register(struct regacc *r); void dump_cp_mem_pool(uint32_t *mempool); struct a6xx_hfi_state {