pan/compiler: don't pass midgard_instruction by value

This is a large struct, so let's pass it by reference instead of by
value.

Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32851>

src/panfrost/midgard/compiler.h

@@ -315,16 +315,17 @@ typedef struct compiler_context {
 /* Append instruction to end of current block */
 
 static inline midgard_instruction *
-mir_upload_ins(struct compiler_context *ctx, struct midgard_instruction ins)
+mir_upload_ins(struct compiler_context *ctx,
+               const struct midgard_instruction *ins)
 {
    midgard_instruction *heap = ralloc(ctx, struct midgard_instruction);
-   memcpy(heap, &ins, sizeof(ins));
+   memcpy(heap, ins, sizeof(*ins));
    return heap;
 }
 
 static inline midgard_instruction *
 emit_mir_instruction(struct compiler_context *ctx,
-                     struct midgard_instruction ins)
+                     const struct midgard_instruction *ins)
 {
    midgard_instruction *u = mir_upload_ins(ctx, ins);
    list_addtail(&u->link, &ctx->current_block->base.instructions);
@@ -334,7 +335,7 @@ emit_mir_instruction(struct compiler_context *ctx,
 static inline struct midgard_instruction *
 mir_insert_instruction_before(struct compiler_context *ctx,
                               struct midgard_instruction *tag,
-                              struct midgard_instruction ins)
+                              const struct midgard_instruction *ins)
 {
    struct midgard_instruction *u = mir_upload_ins(ctx, ins);
    list_addtail(&u->link, &tag->link);
@@ -541,10 +542,10 @@ bool mir_nontrivial_outmod(const midgard_instruction *ins);
 
 midgard_instruction *mir_insert_instruction_before_scheduled(
    compiler_context *ctx, midgard_block *block, const midgard_instruction *tag,
-   midgard_instruction ins);
+   const midgard_instruction *ins);
 midgard_instruction *mir_insert_instruction_after_scheduled(
    compiler_context *ctx, midgard_block *block, const midgard_instruction *tag,
-   midgard_instruction ins);
+   const midgard_instruction *ins);
 void mir_flip(midgard_instruction *ins);
 void mir_compute_temp_count(compiler_context *ctx);
 

src/panfrost/midgard/midgard_compile.c

@@ -92,7 +92,10 @@ schedule_barrier(compiler_context *ctx)
 /* Helpers to generate midgard_instruction's using macro magic, since every
  * driver seems to do it that way */
 
-#define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
+#define EMIT(op, ...) do {                                                     \
+   struct midgard_instruction ins = v_##op(__VA_ARGS__);                       \
+   emit_mir_instruction(ctx, &ins);                                            \
+} while(0)
 
 #define M_LOAD_STORE(name, store, T)                                           \
    static midgard_instruction m_##name(unsigned ssa, unsigned address)         \
@@ -597,7 +600,7 @@ emit_explicit_constant(compiler_context *ctx, unsigned node)
       midgard_instruction ins =
          v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), node);
       attach_constants(ctx, &ins, constant_value, node + 1);
-      emit_mir_instruction(ctx, ins);
+      emit_mir_instruction(ctx, &ins);
    }
 }
 
@@ -1033,7 +1036,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
       ins.is_pack = true;
    }
 
-   emit_mir_instruction(ctx, ins);
+   emit_mir_instruction(ctx, &ins);
 }
 
 #undef ALU_CASE
@@ -1114,7 +1117,7 @@ emit_ubo_read(compiler_context *ctx, nir_instr *instr, unsigned dest,
 
    midgard_pack_ubo_index_imm(&ins.load_store, index);
 
-   return emit_mir_instruction(ctx, ins);
+   return emit_mir_instruction(ctx, &ins);
 }
 
 /* Globals are like UBOs if you squint. And shared memory is like globals if
@@ -1211,7 +1214,7 @@ emit_global(compiler_context *ctx, nir_instr *instr, bool is_read,
          ins.swizzle[0][i] = first_component;
    }
 
-   emit_mir_instruction(ctx, ins);
+   emit_mir_instruction(ctx, &ins);
 }
 
 static midgard_load_store_op
@@ -1290,7 +1293,7 @@ emit_atomic(compiler_context *ctx, nir_intrinsic_instr *instr)
 
    mir_set_intr_mask(&instr->instr, &ins, true);
 
-   emit_mir_instruction(ctx, ins);
+   emit_mir_instruction(ctx, &ins);
 }
 
 static void
@@ -1361,7 +1364,7 @@ emit_varying_read(compiler_context *ctx, unsigned dest, unsigned offset,
                                                         : midgard_op_ld_vary_16;
    }
 
-   emit_mir_instruction(ctx, ins);
+   emit_mir_instruction(ctx, &ins);
 }
 
 static midgard_instruction
@@ -1419,7 +1422,7 @@ emit_image_op(compiler_context *ctx, nir_intrinsic_instr *instr)
    } else
       ins.load_store.index_reg = REGISTER_LDST_ZERO;
 
-   emit_mir_instruction(ctx, ins);
+   emit_mir_instruction(ctx, &ins);
 
    return ins;
 }
@@ -1450,7 +1453,7 @@ emit_attr_read(compiler_context *ctx, unsigned dest, unsigned offset,
       break;
    }
 
-   emit_mir_instruction(ctx, ins);
+   emit_mir_instruction(ctx, &ins);
 }
 
 static unsigned
@@ -1513,7 +1516,7 @@ emit_fragment_store(compiler_context *ctx, unsigned src, unsigned src_z,
    }
 
    /* Emit the branch */
-   br = emit_mir_instruction(ctx, ins);
+   br = emit_mir_instruction(ctx, &ins);
    schedule_barrier(ctx);
    ctx->writeout_branch[rt][sample_iter] = br;
 
@@ -1531,7 +1534,7 @@ emit_compute_builtin(compiler_context *ctx, nir_intrinsic_instr *instr)
    ins.mask = mask_of(3);
    ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
    ins.load_store.arg_reg = compute_builtin_arg(instr->intrinsic);
-   emit_mir_instruction(ctx, ins);
+   emit_mir_instruction(ctx, &ins);
 }
 
 static unsigned
@@ -1568,7 +1571,7 @@ emit_special(compiler_context *ctx, nir_intrinsic_instr *instr, unsigned idx)
    for (int i = 0; i < 4; ++i)
       ld.swizzle[0][i] = COMPONENT_X;
 
-   emit_mir_instruction(ctx, ld);
+   emit_mir_instruction(ctx, &ld);
 }
 
 static void
@@ -1581,7 +1584,7 @@ emit_control_barrier(compiler_context *ctx)
       .op = midgard_tex_op_barrier,
    };
 
-   emit_mir_instruction(ctx, ins);
+   emit_mir_instruction(ctx, &ins);
 }
 
 static uint8_t
@@ -1626,7 +1629,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
       ins.dest_type = ins.src_types[1] = nir_type_uint | instr->def.bit_size;
 
       ins.mask = BITFIELD_MASK(instr->def.num_components);
-      emit_mir_instruction(ctx, ins);
+      emit_mir_instruction(ctx, &ins);
       break;
    }
 
@@ -1641,7 +1644,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
          discard.src_types[0] = nir_type_uint32;
       }
 
-      emit_mir_instruction(ctx, discard);
+      emit_mir_instruction(ctx, &discard);
       schedule_barrier(ctx);
 
       break;
@@ -1720,8 +1723,10 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
 
          if (*input == ~0)
             *input = reg;
-         else
-            emit_mir_instruction(ctx, v_mov(*input, reg));
+         else {
+            struct midgard_instruction ins = v_mov(*input, reg);
+            emit_mir_instruction(ctx, &ins);
+         }
       } else if (ctx->stage == MESA_SHADER_VERTEX) {
          emit_attr_read(ctx, reg, offset, nr_comp, t);
       } else {
@@ -1768,7 +1773,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
          ld.load_store.index_reg = REGISTER_LDST_ZERO;
       }
 
-      emit_mir_instruction(ctx, ld);
+      emit_mir_instruction(ctx, &ld);
       break;
    }
 
@@ -1799,7 +1804,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
          ld.load_store.index_reg = REGISTER_LDST_ZERO;
       }
 
-      emit_mir_instruction(ctx, ld);
+      emit_mir_instruction(ctx, &ld);
       break;
    }
 
@@ -1843,7 +1848,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
             unsigned out = make_compiler_temp(ctx);
 
             midgard_instruction ins = v_mov(reg_2, out);
-            emit_mir_instruction(ctx, ins);
+            emit_mir_instruction(ctx, &ins);
 
             ctx->blend_src1 = out;
          }
@@ -1908,7 +1913,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
                src_component++;
          }
 
-         emit_mir_instruction(ctx, st);
+         emit_mir_instruction(ctx, &st);
       } else {
          unreachable("Unknown store");
       }
@@ -2137,7 +2142,7 @@ set_tex_coord(compiler_context *ctx, nir_tex_instr *instr,
       ld.mask = 0x3; /* xy */
       ld.load_store.bitsize_toggle = true;
       ld.swizzle[1][3] = COMPONENT_X;
-      emit_mir_instruction(ctx, ld);
+      emit_mir_instruction(ctx, &ld);
 
       /* We packed cube coordiates (X,Y,Z) into (X,Y), update the
        * written mask accordingly and decrement the number of
@@ -2172,7 +2177,7 @@ set_tex_coord(compiler_context *ctx, nir_tex_instr *instr,
       mov.mask = 1 << COMPONENT_Z;
       written_mask |= 1 << COMPONENT_Z;
       ins->swizzle[1][COMPONENT_Z] = COMPONENT_Z;
-      emit_mir_instruction(ctx, mov);
+      emit_mir_instruction(ctx, &mov);
    }
 
    /* Texelfetch coordinates uses all four elements (xyz/index) regardless
@@ -2188,7 +2193,7 @@ set_tex_coord(compiler_context *ctx, nir_tex_instr *instr,
          v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), ins->src[1]);
       mov.has_constants = true;
       mov.mask = (written_mask | write_mask) ^ 0xF;
-      emit_mir_instruction(ctx, mov);
+      emit_mir_instruction(ctx, &mov);
       for (unsigned c = 0; c < MIR_VEC_COMPONENTS; c++) {
          if (mov.mask & (1 << c))
             ins->swizzle[1][c] = c;
@@ -2212,7 +2217,7 @@ set_tex_coord(compiler_context *ctx, nir_tex_instr *instr,
       }
 
       mov.mask = write_mask;
-      emit_mir_instruction(ctx, mov);
+      emit_mir_instruction(ctx, &mov);
    }
 }
 
@@ -2308,7 +2313,7 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr,
       }
    }
 
-   emit_mir_instruction(ctx, ins);
+   emit_mir_instruction(ctx, &ins);
 }
 
 static void
@@ -2343,7 +2348,7 @@ emit_jump(compiler_context *ctx, nir_jump_instr *instr)
       struct midgard_instruction br = v_branch(false, false);
       br.branch.target_type = TARGET_BREAK;
       br.branch.target_break = ctx->current_loop_depth;
-      emit_mir_instruction(ctx, br);
+      emit_mir_instruction(ctx, &br);
       break;
    }
 
@@ -2442,9 +2447,9 @@ inline_alu_constants(compiler_context *ctx, midgard_block *block)
                &block->base.instructions, midgard_instruction, link);
 
             if (alu == first) {
-               mir_insert_instruction_before(ctx, alu, ins);
+               mir_insert_instruction_before(ctx, alu, &ins);
             } else {
-               mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
+               mir_insert_instruction_before(ctx, mir_prev_op(alu), &ins);
             }
          }
       }
@@ -2688,7 +2693,7 @@ emit_fragment_epilogue(compiler_context *ctx, unsigned rt, unsigned sample_iter)
    ins.branch.target_block = ctx->block_count - 1;
    ins.constants.u32[0] = br->constants.u32[0];
    memcpy(&ins.src_types, &br->src_types, sizeof(ins.src_types));
-   emit_mir_instruction(ctx, ins);
+   emit_mir_instruction(ctx, &ins);
 
    ctx->current_block->epilogue = true;
    schedule_barrier(ctx);
@@ -2804,7 +2809,7 @@ emit_loop(struct compiler_context *ctx, nir_loop *nloop)
    /* Branch back to loop back */
    struct midgard_instruction br_back = v_branch(false, false);
    br_back.branch.target_block = start_idx;
-   emit_mir_instruction(ctx, br_back);
+   emit_mir_instruction(ctx, &br_back);
 
    /* Mark down that branch in the graph. */
    pan_block_add_successor(&start_block->base, &loop_block->base);
@@ -2942,7 +2947,7 @@ mir_add_writeout_loops(compiler_context *ctx)
             midgard_instruction uncond = v_branch(false, false);
             uncond.branch.target_block = popped;
             uncond.branch.target_type = TARGET_GOTO;
-            emit_mir_instruction(ctx, uncond);
+            emit_mir_instruction(ctx, &uncond);
             pan_block_add_successor(&ctx->current_block->base,
                                     &(mir_get_block(ctx, popped)->base));
             schedule_barrier(ctx);
@@ -3003,7 +3008,7 @@ midgard_compile_shader_nir(nir_shader *nir,
          struct midgard_instruction wait = v_branch(false, false);
          wait.branch.target_type = TARGET_TILEBUF_WAIT;
 
-         emit_mir_instruction(ctx, wait);
+         emit_mir_instruction(ctx, &wait);
 
          ++ctx->instruction_count;
       }

src/panfrost/midgard/midgard_derivatives.c

@@ -123,7 +123,7 @@ midgard_emit_derivatives(compiler_context *ctx, nir_intrinsic_instr *instr)
    };
 
    ins.dest = nir_def_index_with_mask(&instr->def, &ins.mask);
-   emit_mir_instruction(ctx, ins);
+   emit_mir_instruction(ctx, &ins);
 }
 
 void
@@ -161,7 +161,7 @@ midgard_lower_derivatives(compiler_context *ctx, midgard_block *block)
       dup.swizzle[1][1] = dup.swizzle[1][2] = dup.swizzle[1][3] = COMPONENT_W;
 
       /* Insert the new instruction */
-      mir_insert_instruction_before(ctx, mir_next_op(ins), dup);
+      mir_insert_instruction_before(ctx, mir_next_op(ins), &dup);
 
       /* We'll need both instructions to write to the same index, so
        * rewrite to use a register */

src/panfrost/midgard/midgard_opt_perspective.c

@@ -153,7 +153,7 @@ midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block)
             },
       };
 
-      mir_insert_instruction_before(ctx, ins, accel);
+      mir_insert_instruction_before(ctx, ins, &accel);
       mir_remove_instruction(ins);
 
       progress |= true;

src/panfrost/midgard/midgard_ra.c

@@ -296,7 +296,7 @@ mir_lower_special_reads(compiler_context *ctx)
 
                   midgard_instruction *use = mir_next_op(pre_use);
                   assert(use);
-                  mir_insert_instruction_before(ctx, use, m);
+                  mir_insert_instruction_before(ctx, use, &m);
                   mir_rewrite_index_dst_single(pre_use, i, idx);
                } else {
                   if (!mir_has_arg(pre_use, i))
@@ -310,7 +310,7 @@ mir_lower_special_reads(compiler_context *ctx)
                   if (mov == NULL || !mir_is_ssa(i)) {
                      midgard_instruction m = v_mov(i, spill_idx++);
                      m.mask = mask;
-                     mov = mir_insert_instruction_before(ctx, pre_use, m);
+                     mov = mir_insert_instruction_before(ctx, pre_use, &m);
                   } else {
                      mov->mask |= mask;
                   }
@@ -1024,7 +1024,7 @@ mir_spill_register(compiler_context *ctx, unsigned spill_node,
                /* Hint: don't rewrite this node */
                st.hint = true;
 
-               mir_insert_instruction_after_scheduled(ctx, block, ins, st);
+               mir_insert_instruction_after_scheduled(ctx, block, ins, &st);
             } else {
                unsigned bundle = ins->bundle_id;
                unsigned dest =
@@ -1039,7 +1039,7 @@ mir_spill_register(compiler_context *ctx, unsigned spill_node,
                   midgard_instruction read =
                      v_load_store_scratch(dest, spill_slot, false, 0xF);
                   mir_insert_instruction_before_scheduled(ctx, block, ins,
-                                                          read);
+                                                          &read);
                   write_mask = 0xF;
                   last_fill = bundle;
                }
@@ -1078,14 +1078,14 @@ mir_spill_register(compiler_context *ctx, unsigned spill_node,
                   midgard_instruction st =
                      v_load_store_scratch(dest, spill_slot, true, write_mask);
                   last_spill = mir_insert_instruction_after_scheduled(
-                     ctx, block, ins, st);
+                     ctx, block, ins, &st);
                }
 
                if (move) {
                   midgard_instruction mv = v_mov(ins->dest, dest);
                   mv.no_spill |= (1 << spill_class);
 
-                  mir_insert_instruction_after_scheduled(ctx, block, ins, mv);
+                  mir_insert_instruction_after_scheduled(ctx, block, ins, &mv);
                }
 
                last_id = bundle;
@@ -1142,7 +1142,7 @@ mir_spill_register(compiler_context *ctx, unsigned spill_node,
             st.mask =
                mir_from_bytemask(mir_round_bytemask_up(read_bytemask, 32), 32);
 
-            mir_insert_instruction_before_scheduled(ctx, block, before, st);
+            mir_insert_instruction_before_scheduled(ctx, block, before, &st);
          } else {
             /* Special writes already have their move spilled in */
             index = spill_slot;
@@ -1206,7 +1206,7 @@ mir_demote_uniforms(compiler_context *ctx, unsigned new_cutoff)
             midgard_pack_ubo_index_imm(&ld.load_store,
                                        ctx->info->push.words[idx].ubo);
 
-            mir_insert_instruction_before_scheduled(ctx, block, before, ld);
+            mir_insert_instruction_before_scheduled(ctx, block, before, &ld);
 
             mir_rewrite_index_src_single(ins, ins->src[i], temp);
          }

src/panfrost/midgard/midgard_schedule.c

@@ -982,7 +982,7 @@ mir_schedule_comparison(compiler_context *ctx,
    mov.mask = vector ? 0xF : 0x1;
    memcpy(mov.swizzle[1], swizzle, sizeof(mov.swizzle[1]));
 
-   return mir_insert_instruction_before(ctx, user, mov);
+   return mir_insert_instruction_before(ctx, user, &mov);
 }
 
 /* Most generally, we need instructions writing to r31 in the appropriate
@@ -1555,7 +1555,7 @@ mir_lower_ldst(compiler_context *ctx)
          for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; ++c)
             mov.swizzle[1][c] = I->swizzle[s][0];
 
-         mir_insert_instruction_before(ctx, I, mov);
+         mir_insert_instruction_before(ctx, I, &mov);
          I->src[s] = mov.dest;
          I->swizzle[s][0] = 0;
       }
@@ -1590,7 +1590,7 @@ mir_lower_blend_input(compiler_context *ctx)
          midgard_instruction mov = v_mov(src, temp);
          mov.mask = 0xF;
          mov.dest_type = nir_type_uint32;
-         mir_insert_instruction_before(ctx, I, mov);
+         mir_insert_instruction_before(ctx, I, &mov);
          I->src[s] = mov.dest;
       }
    }

src/panfrost/midgard/mir.c

@@ -352,12 +352,12 @@ mir_bytemask_of_read_components(const midgard_instruction *ins, unsigned node)
  * in question */
 
 static midgard_bundle
-mir_bundle_for_op(compiler_context *ctx, midgard_instruction ins)
+mir_bundle_for_op(compiler_context *ctx, const midgard_instruction *ins)
 {
    midgard_instruction *u = mir_upload_ins(ctx, ins);
 
    midgard_bundle bundle = {
-      .tag = ins.type,
+      .tag = ins->type,
       .instruction_count = 1,
       .instructions = {u},
    };
@@ -369,7 +369,7 @@ mir_bundle_for_op(compiler_context *ctx, midgard_instruction ins)
       size_t bytes_emitted = sizeof(uint32_t) + sizeof(midgard_reg_info) +
                              sizeof(midgard_vector_alu);
       bundle.padding = ~(bytes_emitted - 1) & 0xF;
-      bundle.control = ins.type | u->unit;
+      bundle.control = ins->type | u->unit;
    }
 
    return bundle;
@@ -397,7 +397,7 @@ midgard_instruction *
 mir_insert_instruction_before_scheduled(compiler_context *ctx,
                                         midgard_block *block,
                                         const midgard_instruction *tag,
-                                        midgard_instruction ins)
+                                        const midgard_instruction *ins)
 {
    unsigned before = mir_bundle_idx_for_ins(tag, block);
    size_t count = util_dynarray_num_elements(&block->bundles, midgard_bundle);
@@ -422,7 +422,7 @@ midgard_instruction *
 mir_insert_instruction_after_scheduled(compiler_context *ctx,
                                        midgard_block *block,
                                        const midgard_instruction *tag,
-                                       midgard_instruction ins)
+                                       const midgard_instruction *ins)
 {
    /* We need to grow the bundles array to add our new bundle */
    size_t count = util_dynarray_num_elements(&block->bundles, midgard_bundle);

src/panfrost/midgard/mir_promote_uniforms.c

@@ -336,7 +336,7 @@ midgard_promote_uniforms(compiler_context *ctx)
 
          uint16_t rounded = mir_round_bytemask_up(mir_bytemask(ins), type_size);
          mir_set_bytemask(&mov, rounded);
-         mir_insert_instruction_before(ctx, ins, mov);
+         mir_insert_instruction_before(ctx, ins, &mov);
       } else {
          mir_rewrite_index_src(ctx, ins->dest, promoted);
       }