freedreno/a6xx: add a618 support

Signed-off-by: Rob Clark <robdclark@chromium.org>

src/gallium/drivers/freedreno/a6xx/fd6_context.c

@@ -92,6 +92,29 @@ fd6_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
 
 
 	switch (screen->gpu_id) {
+	case 618:
+/*
+GRAS_BIN_CONTROL:
+RB_BIN_CONTROL:
+  - a618 doesn't appear to set .USE_VIZ; also bin size diffs
+
+RB_CCU_CNTL:
+  - 0x3c400004 -> 0x3e400004
+  - 0x10000000 -> 0x08000000
+
+RB_UNKNOWN_8E04:               <-- see stencil-0000.rd.gz
+  - 0x01000000 -> 0x00100000
+
+SP_UNKNOWN_A0F8:
+PC_UNKNOWN_9805:
+  - 0x1 -> 0
+ */
+		fd6_ctx->magic.RB_UNKNOWN_8E04_blit = 0x00100000;
+		fd6_ctx->magic.RB_CCU_CNTL_gmem     = 0x3e400004;
+		fd6_ctx->magic.RB_CCU_CNTL_bypass   = 0x08000000;
+		fd6_ctx->magic.PC_UNKNOWN_9805 = 0x0;
+		fd6_ctx->magic.SP_UNKNOWN_A0F8 = 0x0;
+		break;
 	case 630:
 		fd6_ctx->magic.RB_UNKNOWN_8E04_blit = 0x01000000;
 		// NOTE: newer blob using 0x3c400004, need to revisit:

src/gallium/drivers/freedreno/a6xx/fd6_gmem.c

@@ -801,6 +801,9 @@ fd6_emit_tile_init(struct fd_batch *batch)
 		 * the reset of these cmds:
 		 */
 
+// NOTE a618 not setting .USE_VIZ .. from a quick check on a630, it
+// does not appear that this bit changes much (ie. it isn't actually
+// .USE_VIZ like previous gens)
 		set_bin_size(ring, gmem->bin_w, gmem->bin_h,
 				A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
 

src/gallium/drivers/freedreno/freedreno_screen.c

@@ -904,6 +904,7 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro)
 	case 540:
 		fd5_screen_init(pscreen);
 		break;
+	case 618:
 	case 630:
 		fd6_screen_init(pscreen);
 		break;