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freedreno/a6xx: cleanup magic registers

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Extract out values for the handful of unknown registers which have
different values across different a6xx models, to simplify adding
support for new a6xx's.

Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Rob Clark 2019-10-24 14:03:32 -07:00
parent 1fdc259bfc
commit afd224fac3
6 changed files with 47 additions and 22 deletions
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18
src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
View file

@ -195,7 +195,8 @@ blit_control(enum a6xx_color_fmt fmt)
* supported by hw.. if necessary decompose into (potentially) two 2D blits
*/
static void
emit_blit_buffer(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
emit_blit_buffer(struct fd_context *ctx, struct fd_ringbuffer *ring,
const struct pipe_blit_info *info)
{
const struct pipe_box *sbox = &info->src.box;
const struct pipe_box *dbox = &info->dst.box;
@ -327,7 +328,7 @@ emit_blit_buffer(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
OUT_RING(ring, 0xf180);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
OUT_RING(ring, 0x01000000);
OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
@ -335,12 +336,13 @@ emit_blit_buffer(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
OUT_RING(ring, 0);
OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
}
}
static void
emit_blit_texture(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
emit_blit_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
const struct pipe_blit_info *info)
{
const struct pipe_box *sbox = &info->src.box;
const struct pipe_box *dbox = &info->dst.box;
@ -540,7 +542,7 @@ emit_blit_texture(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
0xf000);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
OUT_RING(ring, 0x01000000);
OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
@ -548,7 +550,7 @@ emit_blit_texture(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
OUT_RING(ring, 0);
OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
}
}
@ -676,12 +678,12 @@ handle_rgba_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
(info->dst.resource->target == PIPE_BUFFER)) {
assert(fd_resource(info->src.resource)->tile_mode == TILE6_LINEAR);
assert(fd_resource(info->dst.resource)->tile_mode == TILE6_LINEAR);
emit_blit_buffer(batch->draw, info);
emit_blit_buffer(ctx, batch->draw, info);
} else {
/* I don't *think* we need to handle blits between buffer <-> !buffer */
debug_assert(info->src.resource->target != PIPE_BUFFER);
debug_assert(info->dst.resource->target != PIPE_BUFFER);
emit_blit_texture(batch->draw, info);
emit_blit_texture(ctx, batch->draw, info);
}
fd6_event_write(batch, batch->draw, 0x1d, true);

12
src/gallium/drivers/freedreno/a6xx/fd6_context.c
View file

@ -90,6 +90,18 @@ fd6_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
if (!fd6_ctx)
return NULL;
switch (screen->gpu_id) {
case 630:
fd6_ctx->magic.RB_UNKNOWN_8E04_blit = 0x01000000;
// NOTE: newer blob using 0x3c400004, need to revisit:
fd6_ctx->magic.RB_CCU_CNTL_gmem = 0x7c400004;
fd6_ctx->magic.RB_CCU_CNTL_bypass = 0x10000000;
fd6_ctx->magic.PC_UNKNOWN_9805 = 0x1;
fd6_ctx->magic.SP_UNKNOWN_A0F8 = 0x1;
break;
}
pctx = &fd6_ctx->base.base;
pctx->screen = pscreen;

12
src/gallium/drivers/freedreno/a6xx/fd6_context.h
View file

@ -91,6 +91,18 @@ struct fd6_context {
uint16_t tex_seqno;
struct hash_table *tex_cache;
/* collection of magic register values which differ between
* various different a6xx
*/
struct {
uint32_t RB_UNKNOWN_8E04_blit; /* value for CP_BLIT's */
uint32_t RB_CCU_CNTL_bypass; /* for sysmem rendering */
uint32_t RB_CCU_CNTL_gmem; /* for GMEM rendering */
uint32_t PC_UNKNOWN_9805;
uint32_t SP_UNKNOWN_A0F8;
} magic;
};
static inline struct fd6_context *

7
src/gallium/drivers/freedreno/a6xx/fd6_draw.c
View file

@ -256,6 +256,7 @@ static void
fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
{
struct fd_ringbuffer *ring;
struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
// TODO mid-frame clears (ie. app doing crazy stuff)?? Maybe worth
// splitting both clear and lrz clear out into their own rb's. And
@ -277,7 +278,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
OUT_RING(ring, 0x10000000);
OUT_RING(ring, fd6_ctx->magic.RB_CCU_CNTL_bypass);
OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
OUT_RING(ring, 0x7ffff);
@ -354,7 +355,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
OUT_RING(ring, 0x1000000);
OUT_RING(ring, fd6_ctx->magic.RB_UNKNOWN_8E04_blit);
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
@ -362,7 +363,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
OUT_RING(ring, 0x0);
OUT_RING(ring, 0x0); /* RB_UNKNOWN_8E04 */
fd6_event_write(batch, ring, UNK_1D, true);
fd6_event_write(batch, ring, FACENESS_FLUSH, true);

3
src/gallium/drivers/freedreno/a6xx/fd6_emit.c
View file

@ -1218,8 +1218,7 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
OUT_WFI5(ring);
WRITE(REG_A6XX_RB_CCU_CNTL, 0x7c400004);
WRITE(REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
WRITE(REG_A6XX_RB_UNKNOWN_8E04, 0x0);
WRITE(REG_A6XX_SP_UNKNOWN_AE04, 0x8);
WRITE(REG_A6XX_SP_UNKNOWN_AE00, 0);
WRITE(REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);

17
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
View file

@ -642,6 +642,7 @@ emit_binning_pass(struct fd_batch *batch)
{
struct fd_ringbuffer *ring = batch->gmem;
struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
uint32_t x1 = gmem->minx;
uint32_t y1 = gmem->miny;
@ -669,10 +670,10 @@ emit_binning_pass(struct fd_batch *batch)
update_vsc_pipe(batch);
OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
OUT_RING(ring, 0x1);
OUT_RING(ring, fd6_ctx->magic.PC_UNKNOWN_9805);
OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
OUT_RING(ring, 0x1);
OUT_RING(ring, fd6_ctx->magic.SP_UNKNOWN_A0F8);
OUT_PKT7(ring, CP_EVENT_WRITE, 1);
OUT_RING(ring, UNK_2C);
@ -717,7 +718,7 @@ emit_binning_pass(struct fd_batch *batch)
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
OUT_RING(ring, 0x7c400004); /* RB_CCU_CNTL */
OUT_RING(ring, fd6_ctx->magic.RB_CCU_CNTL_gmem);
}
static void
@ -771,10 +772,9 @@ fd6_emit_tile_init(struct fd_batch *batch)
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
OUT_RING(ring, 0x0);
/* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
fd_wfi(batch, ring);
OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
OUT_RING(ring, 0x7c400004); /* RB_CCU_CNTL */
OUT_RING(ring, fd6_context(ctx)->magic.RB_CCU_CNTL_gmem);
emit_zs(ring, pfb->zsbuf, &ctx->gmem);
emit_mrt(ring, pfb, &ctx->gmem);
@ -808,10 +808,10 @@ fd6_emit_tile_init(struct fd_batch *batch)
OUT_RING(ring, 0x0);
OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
OUT_RING(ring, 0x1);
OUT_RING(ring, fd6_context(ctx)->magic.PC_UNKNOWN_9805);
OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
OUT_RING(ring, 0x1);
OUT_RING(ring, fd6_context(ctx)->magic.SP_UNKNOWN_A0F8);
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
OUT_RING(ring, 0x1);
@ -1463,10 +1463,9 @@ fd6_emit_sysmem_prep(struct fd_batch *batch)
fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
fd6_cache_inv(batch, ring);
/* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
fd_wfi(batch, ring);
OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */
OUT_RING(ring, fd6_context(batch->ctx)->magic.RB_CCU_CNTL_bypass);
/* enable stream-out, with sysmem there is only one pass: */
OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);