fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-04 00:30:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

ac/surface: move surf_index and fmask_surf_index into ac_addrlib

Browse source 
They don't have to be in drivers.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38093>
This commit is contained in:
Marek Olšák 2025-10-15 03:44:56 -04:00 • committed by Marge Bot
parent 6857fbba59
commit feaa359b43
6 changed files with 11 additions and 32 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

22
src/amd/common/ac_surface.c
View file

@ -87,6 +87,12 @@
struct ac_addrlib {
ADDR_HANDLE handle;
simple_mtx_t lock;
/* Monotonic counters to randomize radeon_surf::tile_swizzle for each allocated image layout.
* radeon_surf::tile_swizzle shuffles image tiles to get random tile order.
*/
uint32_t surf_index;
uint32_t fmask_surf_index;
};
unsigned ac_pipe_config_to_num_pipes(unsigned pipe_config)
@ -1201,14 +1207,8 @@ static bool use_tile_swizzle(const struct ac_surf_config *config, const struct r
bool fmask)
{
if (fmask) {
if (!config->info.fmask_surf_index)
return false;
return !(surf->flags & RADEON_SURF_SHAREABLE);
} else {
if (!config->info.surf_index)
return false;
return surf->modifier == DRM_FORMAT_MOD_INVALID &&
!(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE |
RADEON_SURF_HOST_TRANSFER | RADEON_SURF_DECODE_DST |
@ -1255,7 +1255,7 @@ static int gfx6_surface_settings(struct ac_addrlib *addrlib, const struct radeon
AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT);
AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(&addrlib->surf_index) - 1;
AddrBaseSwizzleIn.tileIndex = csio->tileIndex;
AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex;
AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo;
@ -1818,7 +1818,7 @@ static int gfx6_compute_surface(struct ac_addrlib *addrlib, const struct radeon_
xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT);
/* This counter starts from 1 instead of 0. */
xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
xin.surfIndex = p_atomic_inc_return(&addrlib->fmask_surf_index);
xin.tileIndex = fout.tileIndex;
xin.macroModeIndex = fout.macroModeIndex;
xin.pTileInfo = fout.pTileInfo;
@ -2394,7 +2394,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT);
xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
xin.surfIndex = p_atomic_inc_return(&addrlib->surf_index) - 1;
xin.flags = in->flags;
xin.swizzleMode = in->swizzleMode;
xin.resourceType = in->resourceType;
@ -2595,7 +2595,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_
xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT);
/* This counter starts from 1 instead of 0. */
xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index);
xin.surfIndex = p_atomic_inc_return(&addrlib->fmask_surf_index);
xin.flags = in->flags;
xin.swizzleMode = fin.swizzleMode;
xin.resourceType = in->resourceType;
@ -3445,7 +3445,7 @@ static bool gfx12_compute_miptree(struct ac_addrlib *addrlib, const struct radeo
xin.size = sizeof(ADDR3_COMPUTE_PIPEBANKXOR_INPUT);
xout.size = sizeof(ADDR3_COMPUTE_PIPEBANKXOR_OUTPUT);
xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1;
xin.surfIndex = p_atomic_inc_return(&addrlib->surf_index) - 1;
xin.swizzleMode = in->swizzleMode;
ret = Addr3ComputePipeBankXor(addrlib->handle, &xin, &xout);

2
src/amd/common/ac_surface.h
View file

@ -416,8 +416,6 @@ struct ac_surf_info {
uint8_t levels;
uint8_t num_channels; /* heuristic for displayability */
uint16_t array_size;
uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */
uint32_t *fmask_surf_index;
};
struct ac_surf_config {

7
src/amd/vulkan/radv_device.h
View file

@ -186,13 +186,6 @@ struct radv_device {
/* Backup in-memory cache to be used if the app doesn't provide one */
struct vk_pipeline_cache *mem_cache;
/*
* use different counters so MSAA MRTs get consecutive surface indices,
* even if MASK is allocated in between.
*/
uint32_t image_mrt_offset_counter;
uint32_t fmask_mrt_offset_counter;
struct list_head shader_arenas;
struct hash_table_u64 *capture_replay_arena_vas;
unsigned shader_arena_shift;

3
src/amd/vulkan/radv_image.c
View file

@ -1087,9 +1087,6 @@ radv_get_ac_surf_info(struct radv_device *device, const struct radv_image *image
info.levels = image->vk.mip_levels;
info.num_channels = vk_format_get_nr_components(image->vk.format);
info.surf_index = &device->image_mrt_offset_counter;
info.fmask_surf_index = &device->fmask_mrt_offset_counter;
return info;
}

7
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
View file

@ -77,13 +77,6 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
tex->target == PIPE_TEXTURE_2D_ARRAY ||
tex->target == PIPE_TEXTURE_CUBE_ARRAY;
/* Use different surface counters for color and FMASK, so that MSAA MRTs
* always use consecutive surface indices when FMASK is allocated between
* them.
*/
config.info.surf_index = &aws->surf_index_color;
config.info.fmask_surf_index = &aws->surf_index_fmask;
/* Use radeon_info from the driver, not the winsys. The driver is allowed to change it. */
return ac_compute_surface(aws->addrlib, info, &config, mode, surf);
}

2
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
View file

@ -216,8 +216,6 @@ struct amdgpu_winsys {
simple_mtx_t bo_fence_lock;
int num_cs; /* The number of command streams created. */
uint32_t surf_index_color;
uint32_t surf_index_fmask;
uint32_t next_bo_unique_id;
uint64_t allocated_vram;
uint64_t allocated_gtt;