From feaa359b4302c04637763b4e7fd22370fb93a9c2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 15 Oct 2025 03:44:56 -0400 Subject: [PATCH] ac/surface: move surf_index and fmask_surf_index into ac_addrlib They don't have to be in drivers. Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/common/ac_surface.c | 22 +++++++++---------- src/amd/common/ac_surface.h | 2 -- src/amd/vulkan/radv_device.h | 7 ------ src/amd/vulkan/radv_image.c | 3 --- .../winsys/amdgpu/drm/amdgpu_surface.c | 7 ------ src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h | 2 -- 6 files changed, 11 insertions(+), 32 deletions(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 32fd48fe193..8da1f58fa84 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -87,6 +87,12 @@ struct ac_addrlib { ADDR_HANDLE handle; simple_mtx_t lock; + + /* Monotonic counters to randomize radeon_surf::tile_swizzle for each allocated image layout. + * radeon_surf::tile_swizzle shuffles image tiles to get random tile order. + */ + uint32_t surf_index; + uint32_t fmask_surf_index; }; unsigned ac_pipe_config_to_num_pipes(unsigned pipe_config) @@ -1201,14 +1207,8 @@ static bool use_tile_swizzle(const struct ac_surf_config *config, const struct r bool fmask) { if (fmask) { - if (!config->info.fmask_surf_index) - return false; - return !(surf->flags & RADEON_SURF_SHAREABLE); } else { - if (!config->info.surf_index) - return false; - return surf->modifier == DRM_FORMAT_MOD_INVALID && !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE | RADEON_SURF_HOST_TRANSFER | RADEON_SURF_DECODE_DST | @@ -1255,7 +1255,7 @@ static int gfx6_surface_settings(struct ac_addrlib *addrlib, const struct radeon AddrBaseSwizzleIn.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT); AddrBaseSwizzleOut.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT); - AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1; + AddrBaseSwizzleIn.surfIndex = p_atomic_inc_return(&addrlib->surf_index) - 1; AddrBaseSwizzleIn.tileIndex = csio->tileIndex; AddrBaseSwizzleIn.macroModeIndex = csio->macroModeIndex; AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo; @@ -1818,7 +1818,7 @@ static int gfx6_compute_surface(struct ac_addrlib *addrlib, const struct radeon_ xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT); /* This counter starts from 1 instead of 0. */ - xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index); + xin.surfIndex = p_atomic_inc_return(&addrlib->fmask_surf_index); xin.tileIndex = fout.tileIndex; xin.macroModeIndex = fout.macroModeIndex; xin.pTileInfo = fout.pTileInfo; @@ -2394,7 +2394,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ xin.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_INPUT); xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT); - xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1; + xin.surfIndex = p_atomic_inc_return(&addrlib->surf_index) - 1; xin.flags = in->flags; xin.swizzleMode = in->swizzleMode; xin.resourceType = in->resourceType; @@ -2595,7 +2595,7 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ xout.size = sizeof(ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT); /* This counter starts from 1 instead of 0. */ - xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index); + xin.surfIndex = p_atomic_inc_return(&addrlib->fmask_surf_index); xin.flags = in->flags; xin.swizzleMode = fin.swizzleMode; xin.resourceType = in->resourceType; @@ -3445,7 +3445,7 @@ static bool gfx12_compute_miptree(struct ac_addrlib *addrlib, const struct radeo xin.size = sizeof(ADDR3_COMPUTE_PIPEBANKXOR_INPUT); xout.size = sizeof(ADDR3_COMPUTE_PIPEBANKXOR_OUTPUT); - xin.surfIndex = p_atomic_inc_return(config->info.surf_index) - 1; + xin.surfIndex = p_atomic_inc_return(&addrlib->surf_index) - 1; xin.swizzleMode = in->swizzleMode; ret = Addr3ComputePipeBankXor(addrlib->handle, &xin, &xout); diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index d0383af5a25..0900c3db10b 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -416,8 +416,6 @@ struct ac_surf_info { uint8_t levels; uint8_t num_channels; /* heuristic for displayability */ uint16_t array_size; - uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */ - uint32_t *fmask_surf_index; }; struct ac_surf_config { diff --git a/src/amd/vulkan/radv_device.h b/src/amd/vulkan/radv_device.h index a57a98093a4..9b5dd9352bc 100644 --- a/src/amd/vulkan/radv_device.h +++ b/src/amd/vulkan/radv_device.h @@ -186,13 +186,6 @@ struct radv_device { /* Backup in-memory cache to be used if the app doesn't provide one */ struct vk_pipeline_cache *mem_cache; - /* - * use different counters so MSAA MRTs get consecutive surface indices, - * even if MASK is allocated in between. - */ - uint32_t image_mrt_offset_counter; - uint32_t fmask_mrt_offset_counter; - struct list_head shader_arenas; struct hash_table_u64 *capture_replay_arena_vas; unsigned shader_arena_shift; diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 3508c6adbcb..1380df1c87b 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -1087,9 +1087,6 @@ radv_get_ac_surf_info(struct radv_device *device, const struct radv_image *image info.levels = image->vk.mip_levels; info.num_channels = vk_format_get_nr_components(image->vk.format); - info.surf_index = &device->image_mrt_offset_counter; - info.fmask_surf_index = &device->fmask_mrt_offset_counter; - return info; } diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c index b0f32f0ccfd..b4d7af8e314 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c @@ -77,13 +77,6 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, tex->target == PIPE_TEXTURE_2D_ARRAY || tex->target == PIPE_TEXTURE_CUBE_ARRAY; - /* Use different surface counters for color and FMASK, so that MSAA MRTs - * always use consecutive surface indices when FMASK is allocated between - * them. - */ - config.info.surf_index = &aws->surf_index_color; - config.info.fmask_surf_index = &aws->surf_index_fmask; - /* Use radeon_info from the driver, not the winsys. The driver is allowed to change it. */ return ac_compute_surface(aws->addrlib, info, &config, mode, surf); } diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h index 8cd5924a173..be14f49aca2 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h @@ -216,8 +216,6 @@ struct amdgpu_winsys { simple_mtx_t bo_fence_lock; int num_cs; /* The number of command streams created. */ - uint32_t surf_index_color; - uint32_t surf_index_fmask; uint32_t next_bo_unique_id; uint64_t allocated_vram; uint64_t allocated_gtt;