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brw: Add assembler support for SRND

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Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36529>
This commit is contained in:
Sushma Venkatesh Reddy 2025-07-29 23:31:24 +00:00 • committed by Marge Bot
parent 51f4a2572a
commit fe6d364ca8
2 changed files with 6 additions and 1 deletions
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6
src/intel/compiler/brw_gram.y
View file

@ -235,6 +235,9 @@ i965_asm_binary_instruction(int opcode,
case BRW_OPCODE_MUL:
brw_MUL(p, dest, src0, src1);
break;
case BRW_OPCODE_SRND:
brw_SRND(p, dest, src0, src1);
break;
default:
fprintf(stderr, "Unsupported binary opcode\n");
}
@ -381,7 +384,7 @@ i965_asm_set_instruction_options(struct brw_codegen *p,
%token <integer> OR
%token <integer> PLN POP PUSH
%token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
%token <integer> SEL SENDS SENDSC SHL SHR SMOV SUBB SYNC
%token <integer> SEL SENDS SENDSC SHL SHR SMOV SRND SUBB SYNC
%token <integer> SEND_GFX4 SENDC_GFX4 SEND_GFX12 SENDC_GFX12
%token <integer> WAIT WHILE
%token <integer> XOR
@ -757,6 +760,7 @@ binaryopcodes:
| ROL
| ROR
| SUBB
| SRND
;
/* Binary acc instruction */

1
src/intel/compiler/brw_lex.l
View file

@ -124,6 +124,7 @@ sendsc { yylval.integer = BRW_OPCODE_SENDSC; return SENDSC; }
shl { yylval.integer = BRW_OPCODE_SHL; return SHL; }
shr { yylval.integer = BRW_OPCODE_SHR; return SHR; }
smov { yylval.integer = BRW_OPCODE_SMOV; return SMOV; }
srnd { yylval.integer = BRW_OPCODE_SRND; return SRND; }
subb { yylval.integer = BRW_OPCODE_SUBB; return SUBB; }
wait { yylval.integer = BRW_OPCODE_WAIT; return WAIT; }
while { yylval.integer = BRW_OPCODE_WHILE; return WHILE; }