From fe6d364ca8f6e8d9c684f7b5eac5c39aaee6ab77 Mon Sep 17 00:00:00 2001 From: Sushma Venkatesh Reddy Date: Tue, 29 Jul 2025 23:31:24 +0000 Subject: [PATCH] brw: Add assembler support for SRND Reviewed-by: Caio Oliveira Part-of: --- src/intel/compiler/brw_gram.y | 6 +++++- src/intel/compiler/brw_lex.l | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_gram.y b/src/intel/compiler/brw_gram.y index a19e903204a..e4335f1c750 100644 --- a/src/intel/compiler/brw_gram.y +++ b/src/intel/compiler/brw_gram.y @@ -235,6 +235,9 @@ i965_asm_binary_instruction(int opcode, case BRW_OPCODE_MUL: brw_MUL(p, dest, src0, src1); break; + case BRW_OPCODE_SRND: + brw_SRND(p, dest, src0, src1); + break; default: fprintf(stderr, "Unsupported binary opcode\n"); } @@ -381,7 +384,7 @@ i965_asm_set_instruction_options(struct brw_codegen *p, %token OR %token PLN POP PUSH %token RET RNDD RNDE RNDU RNDZ ROL ROR -%token SEL SENDS SENDSC SHL SHR SMOV SUBB SYNC +%token SEL SENDS SENDSC SHL SHR SMOV SRND SUBB SYNC %token SEND_GFX4 SENDC_GFX4 SEND_GFX12 SENDC_GFX12 %token WAIT WHILE %token XOR @@ -757,6 +760,7 @@ binaryopcodes: | ROL | ROR | SUBB + | SRND ; /* Binary acc instruction */ diff --git a/src/intel/compiler/brw_lex.l b/src/intel/compiler/brw_lex.l index 26c642a636f..bdb36e83162 100644 --- a/src/intel/compiler/brw_lex.l +++ b/src/intel/compiler/brw_lex.l @@ -124,6 +124,7 @@ sendsc { yylval.integer = BRW_OPCODE_SENDSC; return SENDSC; } shl { yylval.integer = BRW_OPCODE_SHL; return SHL; } shr { yylval.integer = BRW_OPCODE_SHR; return SHR; } smov { yylval.integer = BRW_OPCODE_SMOV; return SMOV; } +srnd { yylval.integer = BRW_OPCODE_SRND; return SRND; } subb { yylval.integer = BRW_OPCODE_SUBB; return SUBB; } wait { yylval.integer = BRW_OPCODE_WAIT; return WAIT; } while { yylval.integer = BRW_OPCODE_WHILE; return WHILE; }