fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-05 04:40:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

intel/brw: Make fs_reg an alias of brw_reg

Browse source 
And rename the brw_reg_from_fs_reg() function to something more
appropriate.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29791>
This commit is contained in:
Caio Oliveira 2024-06-18 22:27:44 -07:00 • committed by Marge Bot
parent 69f4ed3102
commit fe46efa647
4 changed files with 18 additions and 20 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
src/intel/compiler/brw_fs.cpp
View file

@ -538,15 +538,6 @@ fs_inst::can_change_types() const
!src[1].abs && !src[1].negate && src[1].file != ATTR));
}
/** Generic unset register constructor. */
fs_reg::fs_reg()
{
memset((void*)this, 0, sizeof(*this));
type = BRW_TYPE_UD;
stride = 1;
this->file = BAD_FILE;
}
bool
brw_reg::equals(const brw_reg &r) const
{

8
src/intel/compiler/brw_fs_generator.cpp
View file

@ -65,8 +65,8 @@ brw_math_function(enum opcode op)
}
static struct brw_reg
brw_reg_from_fs_reg(const struct intel_device_info *devinfo, fs_inst *inst,
fs_reg *reg)
normalize_brw_reg_for_encoding(brw_reg *reg)
{
struct brw_reg brw_reg;
@ -860,7 +860,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
}
for (unsigned int i = 0; i < inst->sources; i++) {
src[i] = brw_reg_from_fs_reg(devinfo, inst, &inst->src[i]);
src[i] = normalize_brw_reg_for_encoding(&inst->src[i]);
/* The accumulator result appears to get used for the
* conditional modifier generation. When negating a UD
* value, there is a 33rd bit generated for the sign in the
@ -871,7 +871,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
inst->src[i].type != BRW_TYPE_UD ||
!inst->src[i].negate);
}
dst = brw_reg_from_fs_reg(devinfo, inst, &inst->dst);
dst = normalize_brw_reg_for_encoding(&inst->dst);
brw_set_default_access_mode(p, BRW_ALIGN_1);
brw_set_default_predicate_control(p, inst->predicate);

6
src/intel/compiler/brw_ir_fs.h
View file

@ -28,11 +28,7 @@
#include "brw_ir.h"
#include "brw_ir_allocator.h"
class fs_reg : public brw_reg {
public:
fs_reg();
fs_reg(struct ::brw_reg reg) : brw_reg(reg) {}
};
using fs_reg = brw_reg;
static inline fs_reg
horiz_offset(const fs_reg &reg, unsigned delta)

15
src/intel/compiler/brw_reg.h
View file

@ -154,7 +154,7 @@ uint32_t brw_swizzle_immediate(enum brw_reg_type type, uint32_t x, unsigned swz)
* WM programs to implement shaders decomposed into "channel serial"
* or "structure of array" form:
*/
struct brw_reg {
typedef struct brw_reg {
union {
struct {
enum brw_reg_type type:5;
@ -195,6 +195,17 @@ struct brw_reg {
uint8_t stride;
#ifdef __cplusplus
/* TODO: Remove this constructor to make this type a POD. To achieve this
* we need to make sure the zero value (currently ARF_NULL) is a good
* replacement for BAD_FILE or make the zero value BAD_FILE.
*/
brw_reg() {
memset((void*)this, 0, sizeof(*this));
this->type = BRW_TYPE_UD;
this->stride = 1;
this->file = BAD_FILE;
}
bool equals(const brw_reg &r) const;
bool negative_equals(const brw_reg &r) const;
bool is_contiguous() const;
@ -211,7 +222,7 @@ struct brw_reg {
*/
unsigned component_size(unsigned width) const;
#endif /* __cplusplus */
};
} brw_reg;
static inline unsigned
phys_nr(const struct intel_device_info *devinfo, const struct brw_reg reg)