fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-23 13:20:14 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

virgl: add offset alignment values to to v2 caps struct

Browse source 
glBindBufferRange(..) in vrend_draw_bind_ubo is failing with
more than one uniform block. This is due to improper alignment
of the start of the second block. Let's query the proper
alignment from the driver and pass it back to Mesa.

Let's query for the texture alignment too, even though the Virgl
renderer doesn't call glTexBufferRange yet.

The default values are the widest workable range possible (for example,
GL_UNIFORM_BUFFER_OFFSET_ALIGNMENT on Nvidia is 256).

Fixes:
	dEQP-GLES3.functional.ubo.* on Nvidia

Example test:
	dEQP-GLES3.functional.ubo.multi_basic_types.single_buffer.shared_vertex

Note: This is based on "virgl: reduce some default capset limits.",
which hasn't landed in Mesa yet but should relatively soon.

Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
gurchetansingh@chromium.org 2018-02-22 18:02:18 -08:00 • committed by Dave Airlie
parent 9283cf2ad1
commit fe0647df5a
3 changed files with 6 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/gallium/drivers/virgl/virgl_hw.h
View file

@ -284,6 +284,8 @@ struct virgl_caps_v2 {
int32_t max_texel_offset; int32_t max_texel_offset;
int32_t min_texture_gather_offset; int32_t min_texture_gather_offset;
int32_t max_texture_gather_offset; int32_t max_texture_gather_offset;
uint32_t texture_buffer_offset_alignment;
uint32_t uniform_buffer_offset_alignment;
}; };
union virgl_caps { union virgl_caps {

4
src/gallium/drivers/virgl/virgl_screen.c
View file

@ -140,7 +140,7 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
case PIPE_CAP_USER_VERTEX_BUFFERS: case PIPE_CAP_USER_VERTEX_BUFFERS:
return 0; return 0;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return 16; return vscreen->caps.caps.v2.uniform_buffer_offset_alignment;
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS: case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
return vscreen->caps.caps.v1.bset.streamout_pause_resume; return vscreen->caps.caps.v1.bset.streamout_pause_resume;
@ -163,7 +163,7 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
return vscreen->caps.caps.v1.max_tbo_size > 0; return vscreen->caps.caps.v1.max_tbo_size > 0;
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
return 0; return vscreen->caps.caps.v2.texture_buffer_offset_alignment;
case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
return 0; return 0;
case PIPE_CAP_CUBE_MAP_ARRAY: case PIPE_CAP_CUBE_MAP_ARRAY:

2
src/gallium/drivers/virgl/virgl_winsys.h
View file

@ -132,5 +132,7 @@ static inline void virgl_ws_fill_new_caps_defaults(struct virgl_drm_caps *caps)
caps->caps.v2.max_texel_offset = 7; caps->caps.v2.max_texel_offset = 7;
caps->caps.v2.min_texture_gather_offset = -8; caps->caps.v2.min_texture_gather_offset = -8;
caps->caps.v2.max_texture_gather_offset = 7; caps->caps.v2.max_texture_gather_offset = 7;
caps->caps.v2.texture_buffer_offset_alignment = 32;
caps->caps.v2.uniform_buffer_offset_alignment = 256;
} }
#endif #endif