fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-27 01:10:25 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

ail: handle >4GiB textures

Browse source 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26614>
This commit is contained in:
Alyssa Rosenzweig 2023-11-20 12:09:40 -04:00
parent 7a7a3b8847
commit fd91d46487
2 changed files with 10 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
src/asahi/layout/layout.c
View file

@ -19,8 +19,8 @@ ail_initialize_linear(struct ail_layout *layout)
assert((layout->linear_stride_B % 16) == 0 && "Strides must be aligned");
/* Layer stride must be cache line aligned to pack linear 2D arrays */
layout->layer_stride_B =
ALIGN_POT(layout->linear_stride_B * layout->height_px, AIL_CACHELINE);
layout->layer_stride_B = align64(
(uint64_t)layout->linear_stride_B * layout->height_px, AIL_CACHELINE);
layout->size_B = layout->layer_stride_B * layout->depth_px;
}
@ -177,7 +177,7 @@ ail_initialize_twiddled(struct ail_layout *layout)
else
layout->layer_stride_B = offset_B;
layout->size_B = layout->layer_stride_B * layout->depth_px;
layout->size_B = (uint64_t)layout->layer_stride_B * layout->depth_px;
}
static void
@ -219,7 +219,8 @@ ail_initialize_compression(struct ail_layout *layout)
}
layout->compression_layer_stride_B = compbuf_B;
layout->size_B += layout->compression_layer_stride_B * layout->depth_px;
layout->size_B +=
(uint64_t)(layout->compression_layer_stride_B * layout->depth_px);
}
void

10
src/asahi/layout/layout.h
View file

@ -85,7 +85,7 @@ struct ail_layout {
*
* If depth_px = 1, the value of this field is UNDEFINED.
*/
uint32_t layer_stride_B;
uint64_t layer_stride_B;
/**
* Whether the layer stride is aligned to the page size or not. The hardware
@ -96,12 +96,12 @@ struct ail_layout {
/**
* Offsets of mip levels within a layer.
*/
uint32_t level_offsets_B[AIL_MAX_MIP_LEVELS];
uint64_t level_offsets_B[AIL_MAX_MIP_LEVELS];
/**
* For the compressed buffer, offsets of mip levels within a layer.
*/
uint32_t level_offsets_compressed_B[AIL_MAX_MIP_LEVELS];
uint64_t level_offsets_compressed_B[AIL_MAX_MIP_LEVELS];
/**
* If tiling is TWIDDLED, the tile size used for each mip level within a
@ -114,10 +114,10 @@ struct ail_layout {
uint32_t metadata_offset_B;
/* Stride between subsequent layers in the compression metadata buffer */
uint32_t compression_layer_stride_B;
uint64_t compression_layer_stride_B;
/* Size of entire texture */
uint32_t size_B;
uint64_t size_B;
/* Must the layout support writeable images? If false, the layout MUST NOT be
* used as a writeable image (either PBE or image atomics).