From fd91d4648745ca3dc1ee8d001ff2a9d80acf6590 Mon Sep 17 00:00:00 2001
From: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Date: Mon, 20 Nov 2023 12:09:40 -0400
Subject: [PATCH] ail: handle >4GiB textures

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26614>
---
 src/asahi/layout/layout.c |  9 +++++----
 src/asahi/layout/layout.h | 10 +++++-----
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/src/asahi/layout/layout.c b/src/asahi/layout/layout.c
index 7829f18e7a2..db813e7fdfc 100644
--- a/src/asahi/layout/layout.c
+++ b/src/asahi/layout/layout.c
@@ -19,8 +19,8 @@ ail_initialize_linear(struct ail_layout *layout)
    assert((layout->linear_stride_B % 16) == 0 && "Strides must be aligned");
 
    /* Layer stride must be cache line aligned to pack linear 2D arrays */
-   layout->layer_stride_B =
-      ALIGN_POT(layout->linear_stride_B * layout->height_px, AIL_CACHELINE);
+   layout->layer_stride_B = align64(
+      (uint64_t)layout->linear_stride_B * layout->height_px, AIL_CACHELINE);
 
    layout->size_B = layout->layer_stride_B * layout->depth_px;
 }
@@ -177,7 +177,7 @@ ail_initialize_twiddled(struct ail_layout *layout)
    else
       layout->layer_stride_B = offset_B;
 
-   layout->size_B = layout->layer_stride_B * layout->depth_px;
+   layout->size_B = (uint64_t)layout->layer_stride_B * layout->depth_px;
 }
 
 static void
@@ -219,7 +219,8 @@ ail_initialize_compression(struct ail_layout *layout)
    }
 
    layout->compression_layer_stride_B = compbuf_B;
-   layout->size_B += layout->compression_layer_stride_B * layout->depth_px;
+   layout->size_B +=
+      (uint64_t)(layout->compression_layer_stride_B * layout->depth_px);
 }
 
 void
diff --git a/src/asahi/layout/layout.h b/src/asahi/layout/layout.h
index 7a54215e211..3f67092535b 100644
--- a/src/asahi/layout/layout.h
+++ b/src/asahi/layout/layout.h
@@ -85,7 +85,7 @@ struct ail_layout {
     *
     * If depth_px = 1, the value of this field is UNDEFINED.
     */
-   uint32_t layer_stride_B;
+   uint64_t layer_stride_B;
 
    /**
     * Whether the layer stride is aligned to the page size or not. The hardware
@@ -96,12 +96,12 @@ struct ail_layout {
    /**
     * Offsets of mip levels within a layer.
     */
-   uint32_t level_offsets_B[AIL_MAX_MIP_LEVELS];
+   uint64_t level_offsets_B[AIL_MAX_MIP_LEVELS];
 
    /**
     * For the compressed buffer, offsets of mip levels within a layer.
     */
-   uint32_t level_offsets_compressed_B[AIL_MAX_MIP_LEVELS];
+   uint64_t level_offsets_compressed_B[AIL_MAX_MIP_LEVELS];
 
    /**
     * If tiling is TWIDDLED, the tile size used for each mip level within a
@@ -114,10 +114,10 @@ struct ail_layout {
    uint32_t metadata_offset_B;
 
    /* Stride between subsequent layers in the compression metadata buffer */
-   uint32_t compression_layer_stride_B;
+   uint64_t compression_layer_stride_B;
 
    /* Size of entire texture */
-   uint32_t size_B;
+   uint64_t size_B;
 
    /* Must the layout support writeable images? If false, the layout MUST NOT be
     * used as a writeable image (either PBE or image atomics).