fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-22 15:40:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

ac: Add sdma_version enum and use it for SDMA features.

Browse source 
The SDMA IP is independent from the GFX IP, so it is technically
wrong to program it based on the GFX level.

This patch adds a new enum for SDMA IP version and uses that
to determine functionality such as compression and sparse
support.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26110>
This commit is contained in:
Timur Kristóf 2023-11-09 13:09:37 +01:00
parent d09ad16fd4
commit fd3cdf28ac
3 changed files with 44 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
src/amd/common/ac_gpu_info.c
View file

@ -1268,11 +1268,16 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->has_export_conflict_bug = info->gfx_level == GFX11;
/* GFX6-8 SDMA can't ignore page faults on unmapped sparse resources. */
info->sdma_supports_sparse = info->gfx_level >= GFX9;
/* Convert the SDMA version in the current GPU to an enum. */
info->sdma_ip_version =
(enum sdma_version)SDMA_VERSION_VALUE(info->ip[AMD_IP_SDMA].ver_major,
info->ip[AMD_IP_SDMA].ver_minor);
/* GFX10+ SDMA supports DCC and HTILE, but Navi 10 has issues with it according to PAL. */
info->sdma_supports_compression = info->gfx_level >= GFX10 && info->family != CHIP_NAVI10;
/* SDMA v1.0-3.x (GFX6-8) can't ignore page faults on unmapped sparse resources. */
info->sdma_supports_sparse = info->sdma_ip_version >= SDMA_4_0;
/* SDMA v5.0+ (GFX10+) supports DCC and HTILE, but Navi 10 has issues with it according to PAL. */
info->sdma_supports_compression = info->sdma_ip_version >= SDMA_5_0 && info->family != CHIP_NAVI10;
/* Get the number of good compute units. */
info->num_cu = 0;

1
src/amd/common/ac_gpu_info.h
View file

@ -194,6 +194,7 @@ struct radeon_info {
} dec_caps, enc_caps;
enum vcn_version vcn_ip_version;
enum sdma_version sdma_ip_version;
/* Kernel & winsys capabilities. */
uint32_t drm_major; /* version */

34
src/amd/common/amd_family.h
View file

@ -202,6 +202,40 @@ enum vcn_version{
VCN_4_0_5,
};
#define SDMA_VERSION_VALUE(major, minor) (((major) << 8) | (minor))
enum sdma_version {
SDMA_UNKNOWN = 0,
/* GFX6 */
SDMA_1_0 = SDMA_VERSION_VALUE(1, 0),
/* GFX7 */
SDMA_2_0 = SDMA_VERSION_VALUE(2, 0),
/* GFX8 */
SDMA_2_4 = SDMA_VERSION_VALUE(2, 4),
SDMA_3_0 = SDMA_VERSION_VALUE(3, 0),
SDMA_3_1 = SDMA_VERSION_VALUE(3, 1),
/* GFX9 */
SDMA_4_0 = SDMA_VERSION_VALUE(4, 0),
SDMA_4_1 = SDMA_VERSION_VALUE(4, 1),
SDMA_4_2 = SDMA_VERSION_VALUE(4, 2),
SDMA_4_4 = SDMA_VERSION_VALUE(4, 4),
/* GFX10 */
SDMA_5_0 = SDMA_VERSION_VALUE(5, 0),
/* GFX10.3 */
SDMA_5_2 = SDMA_VERSION_VALUE(5, 2),
/* GFX11 */
SDMA_6_0 = SDMA_VERSION_VALUE(6, 0),
/* GFX11.5 */
SDMA_6_1 = SDMA_VERSION_VALUE(6, 1),
};
const char *ac_get_family_name(enum radeon_family family);
enum amd_gfx_level ac_get_gfx_level(enum radeon_family family);
unsigned ac_get_family_id(enum radeon_family family);