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i965: Set "Stencil Buffer Enable" bit on Haswell.

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Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kenneth Graunke 2011-09-24 01:45:18 -07:00
parent b4410ac394
commit fc8edbe016
2 changed files with 5 additions and 1 deletions
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1
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -1445,6 +1445,7 @@ enum brw_wm_barycentric_interp_mode {
#define GEN7_3DSTATE_CLEAR_PARAMS 0x7804
#define GEN7_3DSTATE_DEPTH_BUFFER 0x7805
#define GEN7_3DSTATE_STENCIL_BUFFER 0x7806
# define HSW_STENCIL_ENABLED (1 << 31)
#define GEN7_3DSTATE_HIER_DEPTH_BUFFER 0x7807
#define _3DSTATE_CLEAR_PARAMS 0x7910 /* ILK, SNB */

5
src/mesa/drivers/dri/i965/gen7_misc_state.c
View file

@ -139,9 +139,12 @@ static void emit_depthbuffer(struct brw_context *brw)
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
const int enabled = intel->is_haswell ? HSW_STENCIL_ENABLED : 0;
BEGIN_BATCH(3);
OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
OUT_BATCH(stencil_mt->region->pitch * stencil_mt->region->cpp - 1);
OUT_BATCH(enabled |
(stencil_mt->region->pitch * stencil_mt->region->cpp - 1));
OUT_RELOC(stencil_mt->region->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);