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i965: Set Line Stipple enable bit in 3DSTATE_SF for Haswell.

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Apparently this needs to be the same as in 3DSTATE_WM.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kenneth Graunke 2011-09-24 00:42:23 -07:00
parent 1b3a199097
commit b4410ac394
2 changed files with 5 additions and 0 deletions
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2
src/mesa/drivers/dri/i965/brw_defines.h
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@ -1210,6 +1210,8 @@ enum brw_message_target {
*/
/* GEN7/DW1: */
# define GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT 12
/* GEN7/DW2: */
# define HSW_SF_LINE_STIPPLE_ENABLE 14
#define _3DSTATE_SBE 0x781F /* GEN7+ */
/* DW1 */

3
src/mesa/drivers/dri/i965/gen7_sf_state.c
View file

@ -249,6 +249,9 @@ upload_sf_state(struct brw_context *brw)
dw2 |= GEN6_SF_LINE_AA_MODE_TRUE;
dw2 |= GEN6_SF_LINE_END_CAP_WIDTH_1_0;
}
if (ctx->Line.StippleFlag && intel->is_haswell) {
dw2 |= HSW_SF_LINE_STIPPLE_ENABLE;
}
/* FINISHME: Last Pixel Enable? Vertex Sub Pixel Precision Select?
* FINISHME: AA Line Distance Mode?