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i965: Make use of brw_load_register_imm32() helper function

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Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: Nanley Chery <nanley.g.chery@intel.com>
This commit is contained in:
Anuj Phogat 2017-11-13 11:23:51 -08:00
parent 1dc45d75bb
commit fc59546e9a
5 changed files with 19 additions and 40 deletions
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6
src/mesa/drivers/dri/i965/brw_draw.c
View file

@ -242,11 +242,7 @@ brw_emit_prim(struct brw_context *brw,
} else {
brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
prim->indirect_offset + 12);
BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX);
OUT_BATCH(0);
ADVANCE_BATCH();
brw_load_register_imm32(brw, GEN7_3DPRIM_BASE_VERTEX, 0);
}
} else {
indirect_flag = 0;

22
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -86,22 +86,16 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
/* Recommended optimizations for Victim Cache eviction and floating
* point blending.
*/
BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(GEN7_CACHE_MODE_1);
OUT_BATCH(REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE |
GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
ADVANCE_BATCH();
brw_load_register_imm32(brw, GEN7_CACHE_MODE_1,
REG_MASK(GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE) |
REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
GEN9_FLOAT_BLEND_OPTIMIZATION_ENABLE |
GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
if (gen_device_info_is_9lp(devinfo)) {
BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(GEN7_GT_MODE);
OUT_BATCH(GEN9_SUBSLICE_HASHING_MASK_BITS |
GEN9_SUBSLICE_HASHING_16x16);
ADVANCE_BATCH();
brw_load_register_imm32(brw, GEN7_GT_MODE,
GEN9_SUBSLICE_HASHING_MASK_BITS |
GEN9_SUBSLICE_HASHING_16x16);
}
}

17
src/mesa/drivers/dri/i965/gen7_l3_state.c
View file

@ -121,19 +121,14 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
if (devinfo->gen >= 8) {
assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
const unsigned imm_data = ((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
SET_FIELD(cfg->n[GEN_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
/* Set up the L3 partitioning. */
OUT_BATCH(GEN8_L3CNTLREG);
OUT_BATCH((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |
SET_FIELD(cfg->n[GEN_L3P_DC], GEN8_L3CNTLREG_DC_ALLOC) |
SET_FIELD(cfg->n[GEN_L3P_ALL], GEN8_L3CNTLREG_ALL_ALLOC));
ADVANCE_BATCH();
brw_load_register_imm32(brw, GEN8_L3CNTLREG, imm_data);
} else {
assert(!cfg->n[GEN_L3P_ALL]);

6
src/mesa/drivers/dri/i965/gen7_sol_state.c
View file

@ -65,11 +65,7 @@ gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
brw->batch.needs_sol_reset = true;
} else {
for (int i = 0; i < 4; i++) {
BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
OUT_BATCH(0);
ADVANCE_BATCH();
brw_load_register_imm32(brw, GEN7_SO_WRITE_OFFSET(i), 0);
}
}

8
src/mesa/drivers/dri/i965/gen8_depth_state.c
View file

@ -331,11 +331,9 @@ gen8_write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits)
render_cache_flush);
/* CACHE_MODE_1 is a non-privileged register. */
BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(GEN7_CACHE_MODE_1);
OUT_BATCH(GEN8_HIZ_PMA_MASK_BITS | pma_stall_bits);
ADVANCE_BATCH();
brw_load_register_imm32(brw, GEN7_CACHE_MODE_1,
GEN8_HIZ_PMA_MASK_BITS |
pma_stall_bits );
/* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
* Flush bits is often necessary. We do it regardless because it's easier.