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i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW

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Number of dwords in MI_FLUSH_DW changed from 4 to 5 in gen8+.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
This commit is contained in:
Anuj Phogat 2017-11-09 11:30:10 -08:00
parent 6165fda59b
commit 1dc45d75bb
2 changed files with 19 additions and 5 deletions
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7
src/mesa/drivers/dri/i965/brw_pipe_control.c
View file

@ -461,11 +461,14 @@ brw_emit_mi_flush(struct brw_context *brw)
const struct gen_device_info *devinfo = &brw->screen->devinfo;
if (brw->batch.ring == BLT_RING && devinfo->gen >= 6) {
BEGIN_BATCH_BLT(4);
OUT_BATCH(MI_FLUSH_DW | (4 - 2));
const unsigned n_dwords = devinfo->gen >= 8 ? 5 : 4;
BEGIN_BATCH_BLT(n_dwords);
OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
if (n_dwords == 5)
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;

17
src/mesa/drivers/dri/i965/intel_blit.c
View file

@ -101,13 +101,17 @@ set_blitter_tiling(struct brw_context *brw,
bool dst_y_tiled, bool src_y_tiled,
uint32_t *__map)
{
assert(brw->screen->devinfo.gen >= 6);
const struct gen_device_info *devinfo = &brw->screen->devinfo;
const unsigned n_dwords = devinfo->gen >= 8 ? 5 : 4;
assert(devinfo->gen >= 6);
/* Idle the blitter before we update how tiling is interpreted. */
OUT_BATCH(MI_FLUSH_DW | (4 - 2));
OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
if (n_dwords == 5)
OUT_BATCH(0);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(BCS_SWCTRL);
@ -119,7 +123,14 @@ set_blitter_tiling(struct brw_context *brw,
#define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map)
#define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) \
BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0)); \
unsigned set_tiling_batch_size = 0; \
if (dst_y_tiled || src_y_tiled) { \
if (devinfo->gen >= 8) \
set_tiling_batch_size = 16; \
else \
set_tiling_batch_size = 14; \
} \
BEGIN_BATCH_BLT(n + set_tiling_batch_size); \
if (dst_y_tiled || src_y_tiled) \
SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled)