diff --git a/src/freedreno/common/freedreno_dev_info.h b/src/freedreno/common/freedreno_dev_info.h
index 0f33c1fcae3..35e17af644a 100644
--- a/src/freedreno/common/freedreno_dev_info.h
+++ b/src/freedreno/common/freedreno_dev_info.h
@@ -168,6 +168,9 @@ struct fd_dev_info {
       bool supports_double_threadsize;
 
       bool has_sampler_minmax;
+
+      bool broken_ds_ubwc_quirk;
+
       struct {
          uint32_t PC_POWER_CNTL;
          uint32_t TPL1_DBG_ECO_CNTL;
diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py
index 752dc0a651b..babec02142d 100644
--- a/src/freedreno/common/freedreno_devices.py
+++ b/src/freedreno/common/freedreno_devices.py
@@ -403,6 +403,10 @@ a6xx_gen4 = A6XXProps(
         has_per_view_viewport = True,
     )
 
+a6xx_a690_quirk = A6XXProps(
+        broken_ds_ubwc_quirk = True,
+    )
+
 add_gpus([
         GPUId(605), # TODO: Test it, based only on libwrapfake dumps
         GPUId(608), # TODO: Test it, based only on libwrapfake dumps
@@ -710,7 +714,7 @@ add_gpus([
         GPUId(chip_id=0xffff06090000, name="FD690"), # Default no-speedbin fallback
     ], A6xxGPUInfo(
         CHIP.A6XX,
-        [a6xx_base, a6xx_gen4],
+        [a6xx_base, a6xx_gen4, a6xx_a690_quirk],
         num_ccu = 8,
         tile_align_w = 64,
         tile_align_h = 32,
diff --git a/src/freedreno/vulkan/tu_image.cc b/src/freedreno/vulkan/tu_image.cc
index 00134d1c767..f7c3cb71ace 100644
--- a/src/freedreno/vulkan/tu_image.cc
+++ b/src/freedreno/vulkan/tu_image.cc
@@ -349,6 +349,15 @@ ubwc_possible(struct tu_device *device,
       return false;
    }
 
+   /* A690 seem to have broken UBWC for depth/stencil, it requires
+    * depth flushing where we cannot realistically place it, like between
+    * ordinary draw calls writing read/depth. WSL blob seem to use ubwc
+    * sometimes for depth/stencil.
+    */
+   if (info->a6xx.broken_ds_ubwc_quirk &&
+       vk_format_is_depth_or_stencil(format))
+      return false;
+
    /* Disable UBWC for D24S8 on A630 in some cases
     *
     * VK_IMAGE_ASPECT_STENCIL_BIT image view requires to be able to sample