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panfrost: reorder lower_bit_size pass

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nir_lower_int64 may generate 16-bit fexp2 instructions, which need to be
lowered.

Fixes dEQP-VK.spirv_assembly.instruction.compute.convertstof.int64_to_float16_m1234
when shaderFloat16 is enabled in panvk. I don't believe it's possible to
trigger this with mediump, so it's not a bug without shaderFloat16.

Signed-off-by: Benjamin Lee <benjamin.lee@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33637>
This commit is contained in:
Benjamin Lee 2025-02-19 18:00:11 -08:00 • committed by Marge Bot
parent a33cd3def2
commit fb9583cd53
1 changed files with 1 additions and 1 deletions
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2
src/panfrost/compiler/bifrost_compile.c
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@ -5580,10 +5580,10 @@ bifrost_preprocess_nir(nir_shader *nir, unsigned gpu_id)
NIR_PASS(_, nir, nir_lower_ssbo, &ssbo_opts);
NIR_PASS(_, nir, pan_lower_sample_pos);
NIR_PASS(_, nir, nir_lower_bit_size, bi_lower_bit_size, &gpu_id);
NIR_PASS(_, nir, nir_lower_64bit_phis);
NIR_PASS(_, nir, pan_lower_helper_invocation);
NIR_PASS(_, nir, nir_lower_int64);
NIR_PASS(_, nir, nir_lower_bit_size, bi_lower_bit_size, &gpu_id);
NIR_PASS(_, nir, nir_opt_idiv_const, 8);
NIR_PASS(_, nir, nir_lower_idiv,