From fb9583cd53c727cf20e78ebed72a5e439e5accda Mon Sep 17 00:00:00 2001 From: Benjamin Lee Date: Wed, 19 Feb 2025 18:00:11 -0800 Subject: [PATCH] panfrost: reorder lower_bit_size pass nir_lower_int64 may generate 16-bit fexp2 instructions, which need to be lowered. Fixes dEQP-VK.spirv_assembly.instruction.compute.convertstof.int64_to_float16_m1234 when shaderFloat16 is enabled in panvk. I don't believe it's possible to trigger this with mediump, so it's not a bug without shaderFloat16. Signed-off-by: Benjamin Lee Reviewed-by: Boris Brezillon Acked-by: Rebecca Mckeever Part-of: --- src/panfrost/compiler/bifrost_compile.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/panfrost/compiler/bifrost_compile.c b/src/panfrost/compiler/bifrost_compile.c index f5715c53738..3e450d8c81f 100644 --- a/src/panfrost/compiler/bifrost_compile.c +++ b/src/panfrost/compiler/bifrost_compile.c @@ -5580,10 +5580,10 @@ bifrost_preprocess_nir(nir_shader *nir, unsigned gpu_id) NIR_PASS(_, nir, nir_lower_ssbo, &ssbo_opts); NIR_PASS(_, nir, pan_lower_sample_pos); - NIR_PASS(_, nir, nir_lower_bit_size, bi_lower_bit_size, &gpu_id); NIR_PASS(_, nir, nir_lower_64bit_phis); NIR_PASS(_, nir, pan_lower_helper_invocation); NIR_PASS(_, nir, nir_lower_int64); + NIR_PASS(_, nir, nir_lower_bit_size, bi_lower_bit_size, &gpu_id); NIR_PASS(_, nir, nir_opt_idiv_const, 8); NIR_PASS(_, nir, nir_lower_idiv,