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asahi: cleanup fs epilog link info

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29179>
This commit is contained in:
Alyssa Rosenzweig 2024-04-07 16:52:04 -04:00 • committed by Marge Bot
parent 71692a5d0b
commit fadb990463
3 changed files with 13 additions and 15 deletions
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5
src/asahi/lib/agx_linker.h
View file

@ -121,12 +121,13 @@ struct agx_fs_epilog_link_info {
* This happens in the epilog for correctness when the epilog discards.
*/
bool write_z, write_s;
};
struct agx_fs_epilog_key {
/* Mask of render targets written by the main shader */
uint8_t rt_written;
};
static_assert(sizeof(struct agx_fs_epilog_link_info) == 8, "packed");
struct agx_fs_epilog_key {
struct agx_fs_epilog_link_info link;
/* Blend state. Blending happens in the epilog. */

15
src/asahi/lib/agx_nir_prolog_epilog.c
View file

@ -290,7 +290,7 @@ agx_nir_fs_epilog(nir_builder *b, const void *key_)
/* First, construct a passthrough shader reading each colour and outputting
* the value.
*/
u_foreach_bit(rt, key->rt_written) {
u_foreach_bit(rt, key->link.rt_written) {
bool dual_src = (rt == 1) && blend_uses_2src(key->blend.rt[0]);
unsigned read_rt = (key->link.broadcast_rt0 && !dual_src) ? 0 : rt;
unsigned size = (key->link.size_32 & BITFIELD_BIT(read_rt)) ? 32 : 16;
@ -461,6 +461,7 @@ lower_output_to_epilog(nir_builder *b, nir_intrinsic_instr *intr, void *data)
if (sem.location == FRAG_RESULT_COLOR) {
sem.location = FRAG_RESULT_DATA0;
info->broadcast_rt0 = true;
info->rt_written = ~0;
}
/* We don't use the epilog for sample mask writes */
@ -475,9 +476,10 @@ lower_output_to_epilog(nir_builder *b, nir_intrinsic_instr *intr, void *data)
if (sem.dual_source_blend_index) {
assert(rt == 0);
rt = 1;
b->shader->info.outputs_written |= BITFIELD64_BIT(FRAG_RESULT_DATA1);
}
info->rt_written |= BITFIELD_BIT(rt);
b->cursor = nir_instr_remove(&intr->instr);
nir_def *vec = intr->src[0].ssa;
@ -509,9 +511,12 @@ bool
agx_nir_lower_fs_output_to_epilog(nir_shader *s,
struct agx_fs_epilog_link_info *out)
{
return nir_shader_intrinsics_pass(
s, lower_output_to_epilog,
nir_metadata_dominance | nir_metadata_block_index, out);
nir_shader_intrinsics_pass(s, lower_output_to_epilog,
nir_metadata_dominance | nir_metadata_block_index,
out);
out->sample_shading = s->info.fs.uses_sample_shading;
return true;
}
bool

8
src/gallium/drivers/asahi/agx_state.c
View file

@ -1796,18 +1796,11 @@ agx_compile_variant(struct agx_device *dev, struct pipe_context *pctx,
attrib_components_read);
if (so->type == PIPE_SHADER_FRAGMENT) {
epilog_key.sample_shading = nir->info.fs.uses_sample_shading;
/* XXX: don't replicate this all over the driver */
epilog_key.rt_spill_base = BITSET_LAST_BIT(nir->info.textures_used) +
(2 * BITSET_LAST_BIT(nir->info.images_used));
compiled->epilog_key = epilog_key;
if (epilog_key.broadcast_rt0)
outputs = ~0;
else
outputs = nir->info.outputs_written >> FRAG_RESULT_DATA0;
}
compiled->so = so;
@ -2428,7 +2421,6 @@ agx_update_fs(struct agx_batch *batch)
.epilog.fs.nr_samples = nr_samples,
.epilog.fs.link = ctx->fs->epilog_key,
.epilog.fs.rt_written = ctx->fs->b.info.outputs,
.epilog.fs.force_small_tile = dev->debug & AGX_DBG_SMALLTILE,
.main = ctx->fs,